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IEEE Transactions on Applied Superconductivity

Superconducting direct digital synthesizer

A. Spooner, Binneg Y. Lao, Dave Rowe, C. Harper, S. Schwarzbek, D.J. Durand, Larry R. Eaton, Andrew D. Smith

Published Jun 1, 1997• 6 citations

Abstract

Communications transmitters, receivers, radar applications, and related test equipment require precise control over generated frequencies which can be provided by digital synthesis. Superconductivity technology offers to greatly improve the operational frequency range at a tiny fraction of the power of present GaAs and Si digital frequency synthesizers, an important consideration for systems with multiple receiver elements and satellite applications. We designed, fabricated, and tested a digital superconducting frequency synthesizer on a 1-cm square substrate in niobium technology and tested at 4 Kelvin. The chip contains a 12-bit pipelined MVTL incremental phase accumulator (simple expansion to 32 bits achieves one part in 4.3/spl times/10/sup 9/ frequency resolution). The most significant 10-bits of the accumulated phase proceed to a Sine ROM which is based on SQUID cells and employs data compression to minimize circuit size. An 8-bit ROM output word proceeds to a superconducting D/A converter to construct the analog output waveform which updates each clock cycle. We have operated the entire superconducting synthesizer above 1 GHz. Our performance goal with present fabrication technology is /spl ges/4 GHz operation.

DOI: 10.1109/77.621691

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Last year we presented the first fully operational superconducting Analog-to-Digital Converter (ADC) with on-chip Digital Signal Processing (DSP). Here we review this device and introduce completed and prospective innovations required to exceed the performance of the best semiconductor counterparts. The ADC chip contains 2 basic parts: a "fundamental" ADC operating at about 20 GHz sampling rate and a digital decimation filter which attenuates high-frequency noise components and reduces the sampling rate to match it with the bandwidth of an input signal. Our short term goal is to achieve 14 bits Spurious Free Dynamic Range (SFDR) for 60 MHz signal bandwidth by using the standard 1000 A/cm/sup 2/ Nb-trilayer fabrication technology commercially available at HYPRES, Inc.

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This paper describes the design, analysis and test results for a 4-bit pseudo-random bit-sequence generator (PRBSG) implemented with complementary output switching logic (COSL) gates. The PRBSG was optimized using a Monte Carlo simulation method for 10-GHz operation. The circuit has been fabricated using niobium technology with critical current density of 1 kA/cm/sup 2/ and sheet resistance of 1 /spl Omega//sq. The 4-bit PRBSG consists of 12 gates and its area is 1530/spl times/950 /spl mu/m/sup 2/. It has been fully tested with a three-phase power supply, and its power consumption is 0.15 mW. The correct operations have been verified experimentally at clock frequencies of up to 2 GHz.