This paper describes the design, analysis and test results for a 4-bit pseudo-random bit-sequence generator (PRBSG) implemented with complementary output switching logic (COSL) gates. The PRBSG was optimized using a Monte Carlo simulation method for 10-GHz operation. The circuit has been fabricated using niobium technology with critical current density of 1 kA/cm/sup 2/ and sheet resistance of 1 /spl Omega//sq. The 4-bit PRBSG consists of 12 gates and its area is 1530/spl times/950 /spl mu/m/sup 2/. It has been fully tested with a three-phase power supply, and its power consumption is 0.15 mW. The correct operations have been verified experimentally at clock frequencies of up to 2 GHz.
This paper describes the design, analysis and test results for a 4-bit pseudo-random bit-sequence generator (PRBSG) implemented with complementary output switching logic (COSL) gates. The PRBSG was optimized using a Monte Carlo simulation method for 10-GHz operation. The circuit has been fabricated using niobium technology with critical current density of 1 kA/cm/sup 2/ and sheet resistance of 1 /spl Omega//sq. The 4-bit PRBSG consists of 12 gates and its area is 1530/spl times/950 /spl mu/m/sup 2/. It has been fully tested with a three-phase power supply, and its power consumption is 0.15 mW. The correct operations have been verified experimentally at clock frequencies of up to 2 GHz.
The development of a new superconducting logic family, complementary output switching logic (COSL), is described. It is described how the two main problems inhibiting superconducting operation at microwave frequencies, namely magnetic flux trapping and large variations of the nominal component values due to the fabrication process, are solved. A brief overview of the operation of the basic logic gate and the layout process is given. Measured results of the basic gates are given for frequencies up to 18 GHz. The measured results of more complex circuits, such as a code converter and a pseudo-random bit sequence generator, are also presented.
Maximum-length sequences (M-sequences) are known as pseudo random numbers generated with relatively simple digital circuits. In this paper, we present a 4-bit M-sequence generator designed and fabricated using a single-flux-quantum (SFQ) logic library and a niobium integration technology. To enhance its generation rate, we have introduced a parallelization scheme where three bits are simultaneously generated in one clock operation. The circuit comprises three exclusive ORs, one delay flip-flop, two dc/SFQ converters (for SET and CLOCK signals), and three SFQ/dc converters (for three parallel outputs). A 10-GHz clock generator of 13 bits is also implemented for high speed testing. The total number of Nb/AlOx/Nb Josephson junctions is 568. Verilog simulation has demonstrated correct circuit operation at 20-GHz clock, which corresponds to the generation rate of 60 Gb/s. The measurement was carried out in a liquid helium bath with double μ-metal cans. Low speed testing with a 1-kHz clock demonstrated periodic signals of three parallelized 4-bit M-sequence; (0, 1, 0), (1, 1, 1), (1, 0, 0), (0, 1, 0), and (0, 1, 1), where (out1, out2, out3) represents the signals from the output ports. We also confirmed that the output signals were correctly shifted when 10-GHz clocks of 13 bits were fed between two 1-kHz clock signals.
Simple RSFQ gates can be very robust, and operate up to high clock speeds in simulation. Larger RSFQ circuits are generally much more limited in clock speed. We believe that this is partly due to less than optimal choice of the timing inter-connections between gates. Timing design is especially problematic for circuits including data loops (feedback). We have developed a new technique for timing design of RSFQ data loops which may be called "balanced skew clock scheduling." It involves equalizing the minimum clock period between every pair of gates. Mathematical analysis proves the optimality of this scheme and reveals the global timing constraints unique to RSFQ data loops. We used this technique for the design of a simple useful clocked RSFQ circuit, a four-bit pseudo-random number generator (PRNG). Constructed from our standard library cells for a 3.5 /spl mu/m 1000 A/cm/sup 2/ Nb-trilayer process, the PRNG worked up to 50 GHz in Jspice simulation.
Communications transmitters, receivers, radar applications, and related test equipment require precise control over generated frequencies which can be provided by digital synthesis. Superconductivity technology offers to greatly improve the operational frequency range at a tiny fraction of the power of present GaAs and Si digital frequency synthesizers, an important consideration for systems with multiple receiver elements and satellite applications. We designed, fabricated, and tested a digital superconducting frequency synthesizer on a 1-cm square substrate in niobium technology and tested at 4 Kelvin. The chip contains a 12-bit pipelined MVTL incremental phase accumulator (simple expansion to 32 bits achieves one part in 4.3/spl times/10/sup 9/ frequency resolution). The most significant 10-bits of the accumulated phase proceed to a Sine ROM which is based on SQUID cells and employs data compression to minimize circuit size. An 8-bit ROM output word proceeds to a superconducting D/A converter to construct the analog output waveform which updates each clock cycle. We have operated the entire superconducting synthesizer above 1 GHz. Our performance goal with present fabrication technology is /spl ges/4 GHz operation.
Maximum-length sequences (M-sequences) are known as pseudo-random numbers generated with relatively simple digital circuits. In this paper, we present a single-flux-quantum digital circuit that generated three output bits of a 4-bit M-sequence in one clock operation. The circuit comprised three clocked exclusive-or gates, one delay flip-flop, three dc/SFQ converters (for set, reset, and low-frequency clock signals), and three SFQ/dc converters (for three parallel outputs), all of which were integrated on a superconducting Nb chip. A 10-GHz clock generator was also implemented for high-speed testing. The total number of Nb/AlOx/Nb Josephson junctions was 568. Verilog simulation demonstrated correct circuit operation with a 20-GHz clock, which corresponded to the generation rate of 60 Gb/s. The measurement was carried out in a liquid helium bath. Low-speed testing with a 1-kHz clock demonstrated periodic signals of three parallelized 4-bit M-sequence. We also confirmed that the outputs were correctly shifted when 13 clock signals of 10 GHz were fed between two 1-kHz clock signals.
Experimental superconducting shift registers consisting of on-chip clock generators, clock regeneration and distribution circuits, shift register elements, and readout circuits are designed using rapid single flux quantum logic/memory (RSFQ) gates. A 7-b shift register has been tested to 12 GHz and a 17-b to 21 GHz using external triggering clocks with relative delay measurements. Testing with internal clocks generated from Josephson oscillations shows a potential high-speed operation of 45 GHz for the 7-b and 30 GHz for the 17-b shift registers. Two types of magnetically coupled readout gates are discussed. The chips are fabricated using a Nb/AlO/sub /x/Nb Josephson-junction process at a critical-current density of 1000 A/cm/sup 2/. The power dissipation per bit is 3 mu W.>