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South African Symposium on Communications and Signal Processing (COMSIG)

Complementary output switching logic: a superconducting voltage-state logic family operating at microwave frequencies

Willem Jakobus Perold

Published Nov 27, 2002• 1 citation
Publisher

Abstract

The development of a new superconducting logic family, complementary output switching logic (COSL), is described. It is described how the two main problems inhibiting superconducting operation at microwave frequencies, namely magnetic flux trapping and large variations of the nominal component values due to the fabrication process, are solved. A brief overview of the operation of the basic logic gate and the layout process is given. Measured results of the basic gates are given for frequencies up to 18 GHz. The measured results of more complex circuits, such as a code converter and a pseudo-random bit sequence generator, are also presented.

DOI
10.1109/comsig.1998.736999

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The development of a new superconducting logic family, complementary output switching logic (COSL), is described. It is described how the two main problems inhibiting superconducting operation at microwave frequencies, namely magnetic flux trapping and large variations of the nominal component values due to the fabrication process, are solved. A brief overview of the operation of the basic logic gate and the layout process is given. Measured results of the basic gates are given for frequencies up to 18 GHz. The measured results of more complex circuits, such as a code converter and a pseudo-random bit sequence generator, are also presented.
This paper describes the design, analysis and test results for a 4-bit pseudo-random bit-sequence generator (PRBSG) implemented with complementary output switching logic (COSL) gates. The PRBSG was optimized using a Monte Carlo simulation method for 10-GHz operation. The circuit has been fabricated using niobium technology with critical current density of 1 kA/cm/sup 2/ and sheet resistance of 1 /spl Omega//sq. The 4-bit PRBSG consists of 12 gates and its area is 1530/spl times/950 /spl mu/m/sup 2/. It has been fully tested with a three-phase power supply, and its power consumption is 0.15 mW. The correct operations have been verified experimentally at clock frequencies of up to 2 GHz.
Complimentary Medal-Oxide Semiconductor (CMOS) technology is expected to soon reach its fundamental limits of operation. The fundamental speed limit of about 4 GHz has already effectively been sidestepped by parallelization. This increases raw processing power but does nothing to improve power dissipation or latency. One approach for increasing computing performance involves using superconducting digital logic circuits. In this thesis I describe a new kind of superconducting logic, invented by Quentin Herr at Northrop Grumman, which uses reciprocal pairs of quantized single magnetic flux pulses to encode classical bits. In Reciprocal Quantum Logic (RQL) the data is encoded in integer units of the magnetic flux quantum. RQL gates operate without the bias resistors of previous superconducting logic families and dissipate several orders of magnitude less power. I demonstrate the basic operation of key RQL gates (AndOr, AnotB, Set/Reset) and show their self-resetting properties. Together, these gates form a universal logic set and provide memory capabilities. Experiments measuring the bit error rate of the AndOr gate extrapolated a minimum BER of 10−480 and a BER of 10−44 with 30% margins on flux biasing. I describe an analytic timing model for RQL gates which demonstrates the self-correcting timing features. From this model I derive equations for the timing behavior and operating limits. Using this timing model I ran simulations to determine correction factions for more accurate predictions at higher frequencies. Using these results, I also develop Very High Speed Integrated Circuit (VHSIC) Hardware Description Language (VHDL) models to describe the combinational logic of RQL gates. To test the timing predictions of the timing model, I performed three experiments on Nb/AlOx/Nb circuits at 4.2 K. The first measured the time of output. The second measured the operating margins of the circuit. The third measured the maximum frequency of operation for RQL circuits. Together, these three experiments showed quantitative agreement with the model for the timing output, qualitative agreement with the limits of operation, and a projected speed limit of 50 GHz for the Hypres 4.5 kA/cm2 process. To power RQL circuits I describe a new design for power splitters and combiners which minimize standing waves. I describe a new kind of Wilkinson power splitter which required numerical optimization but proved to be adequate. I experimentally tested two new designs of the power splitter. Both showed less than 10% variation in standing waves between power splitter and combiner, making it adequate for RQL circuits. I also compared these results with the S-parameters of the power network, which also indicated that the design was adequate for RQL circuits. Finally, I tested an 8-bit Kogge-Stone architecture carry-look ahead adder designed using VHDL models. The adder contained 815 Josephson junctions and was fully functional at 6.21 GHz with a latency of 1.25 clock cycles. The adder produced the correct logical output, had a measured optimal operating point within 8% of the optimal simulated operating point, and measured power margins of 1 dB. It operated best at the designed clock amplitude of 0.88 Ic and dissipated 0.570 mW of power.
Quantum electronic circuits where the logic information is processed and stored in single flux quanta promise efficient computation in a performance/power metric, and thus are of utmost interest as possible replacement or enhancement of CMOS. Several electronic device families leverage superconducting materials and transitions between resistive and superconducting states. Information is coded into bits with deterministic values - as opposed to qubits used in quantum computing. As an example, information can be coded into pulses. Logic gates can be modeled as finite-state machines, that emit logic outputs in response to inputs. The most natural realization of such circuits is through synchronous implementations, where a clock stimulus is transmitted to every logic gate and where logic depth is balanced at every input to achieve full synchrony. Novel superconducting realization families try to go beyond the limitations of synchronous logic with approaches reminiscent of asynchronous design style and leveraging information coding. Moreover, some superconducting families exploit adiabatic operation, in the search for minimizing energy consumption. Design automation for quantum electronic logic families is still in its infancy, but important results have been achieved in terms of automatic balancing and fanout management. The combination of these problems with logic restructuring poses new challenges, as the overall problem is more complex as compared to CMOS and algorithms and tools cannot be just adapted. This presentation will cover recent advancement in design automation for superconducting electronic circuits as well as address future developments in the field.
Superconductive electronics offers a unique combination of high bandwidth and low power for mission critical hardware such as digital processors at 20 to 100 GHz, microwatt per bit analog to digital converters, large digital switches at multi-Gb/s data rates, and low noise parametric amplifiers. This cryogenic technology, typically operating at a few degrees or a few tens of degrees Kelvin, depends upon the unique physics of superconducting materials such as Nb, NbN, and YBaCuO, and the fundamental circuit element, the Josephson junction (JJ) to create unique architectures of unprecedented design efficiency and performance. These circuits are based on the single flux quantum (SFQ) logic family, a technology that has no parallel in semiconductor electronics. Digital data is transmitted by voltage pulses with amplitude less than 1 mV, but at extremely high speeds. Individual gates have been operated as high as 370 GHz. In this paper, we present a brief overview of superconductive digital technology, describe some recent circuits, and discuss how the challenges to superconductive technology are being met, including the use of multi-chip module (MCM) technology, and the potential use of III-V HBT and HEMT circuits to provide interface drivers and amplifiers, possibly operated cryogenically.
This work addresses new signal processing circuits using the special features of superconductivity. A novel flash-type analog-to-digital converter based on a comparator invented in the preceding contract period was demonstrated. The comparator was shown to be useful as a logic gate and an encoder was designed with it. A high-resolution delta-sigma analog-to-digital converter was devised with superconductive components in spite of the lack of an analog integrator in this technology. Positive theoretical results are being followed up experimentally. A simple flux-shuttle single-flux-quantum shift register was devised and several different readout schemes were studied. A six- bit-long version was successfully tested at 1 GHz. A decoder that takes in a five-bit word to select one of 32 output lines was completed. The design involved very tight limitations on current and power. The decoder was combined with a serial-to-parallel converter and operated at 2 GHz. A study of the appropriate architectures for various types of superconductive or Josephson digital technology was developed: an inductance-extraction program.