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IEEE Transactions on Applied Superconductivity

The Effects of a DC Power Layer in a 10-Nb-Layer Device for SFQ LSIs

Hiroyuki Akaike, Keisuke Shigehara, Akira Fujimaki, T. Satoh, K. Hinode, Shuichi Nagasawa, Mutsuo Hidaka

Published Jun 1, 2009• 8 citations
Publisher

Abstract

We have evaluated the effects of a DC power (DCP) layer in a 10-Nb-layer device using SQUIDs and large-scale Josephson transmission lines (LS-JTLs). The 10-Nb-layer device has recently been developed for SFQ LSIs, with an active layer including Josephson junctions (JJs) at the top, two passive transmission line layers in the middle, and the DCP layer for bias current feeds at the bottom. The evaluation with SQUIDs revealed that the 10-Nb-layer device structure drastically reduced the magnetic flux induced by DC currents flowing through the DCP line, in comparison with the previous advanced process device structure. A major factor for this reduction was an increase in the number of ground layers between the DCP layer and the active layer. In the test of the LS-JTLs containing about 12000 JJs, we obtained the operating margins as wide as numerically simulated ones. We also observed no difference in the margins between a method for extracting ground return currents through ground layers and that through the dedicated layer. These results demonstrated that the 10-Nb-layer device structure is suitable for SFQ-LSIs.

DOI
10.1109/tasc.2009.2018033

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We have evaluated the effects of a DC power (DCP) layer in a 10-Nb-layer device using SQUIDs and large-scale Josephson transmission lines (LS-JTLs). The 10-Nb-layer device has recently been developed for SFQ LSIs, with an active layer including Josephson junctions (JJs) at the top, two passive transmission line layers in the middle, and the DCP layer for bias current feeds at the bottom. The evaluation with SQUIDs revealed that the 10-Nb-layer device structure drastically reduced the magnetic flux induced by DC currents flowing through the DCP line, in comparison with the previous advanced process device structure. A major factor for this reduction was an increase in the number of ground layers between the DCP layer and the active layer. In the test of the LS-JTLs containing about 12000 JJs, we obtained the operating margins as wide as numerically simulated ones. We also observed no difference in the margins between a method for extracting ground return currents through ground layers and that through the dedicated layer. These results demonstrated that the 10-Nb-layer device structure is suitable for SFQ-LSIs.
Large-scale SFQ integrated circuits require a large amount of dc-bias current. The magnetic fields induced by the dc-bias currents and the return currents flowing in a ground plane have a great influence on the performance of SFQ circuits. As an approach to reduce the influence, the dc-power (DCP) layer placed under a ground plane is newly introduced in SRL advanced Nb process. We have experimentally evaluated the effects of the DCP layer using SQUIDs and large-scale Josephson transmission line (JTL) circuits with more than 10,000 junctions. The SQUIDs showed that there was small magnetic flux coupling between the DCP lines and themselves and that the coupled flux was enhanced by the return current. The coupled flux decreased with increasing line width of the DCP lines and with increasing distance from the centerlines of them. In the large-scale JTL tests, the cells with DCP patterns showed wider operating margins than the CONNECT OPEN cells with partial magnetic shielding of bias current lines. The test results also showed that a line shape along the periphery of a cell was more effective than a plane shape within a cell as a DCP layer pattern for bias current feeds.
Magnetic isolation is an important issue in the realization of superconducting LSIs including more than ten thousands Josephson junctions. In this paper, we present mutual inductances of two superconducting strip lines coupled through a grounded shield layer. A conventional dc-superconducting quantum interference device (dc-SQUID) method on Nb/AlO x /Nb Josephson IC chips is employed. We have tested one dc-SQUID layout with a floating shield layer for reference, and ten dc-SQUID layouts with grounded shield layers. Four superconducting niobium layers are used as a ground plane, a SQUID line, a shield layer, and a control line from bottom to top. We have confirmed that the number, positions, and dimensions of ground contacts make differences in the mutual inductances. Ground contacts should be placed to enhance the shielding current for effective magnetic isolation.
We have investigated the effect of a dc-power (DCP) layer on the performance of single flux quantum (SFQ) circuits by changing the film thickness of a ground plane (GP). The DCP layer was placed below the GP and was used as bias current feeds. Two measurements were conducted. One was direct detection of the magnetic flux above the GP by using SQUIDs. The results indicated that the GPs with film thicknesses of more than 400 nm were effective to completely suppress the flux under the condition that the return current was extracted from the ground plane. The other was evaluation of the operating margins of the 408 bit shift register circuits (SRs) with 8032 Josephson junctions and a total designed bias current of 1.05 A. The results showed that a 500 nm thick GP had an advantage over a 300 nm thick GP in the dependence of the upper margin on the bias current port of the SR.
We describe the recent progress on a Nb nine-layer fabrication process for large-scale single flux quantum (SFQ) circuits. A device fabricated in this process is composed of an active layer including Josephson junctions (JJ) at the top, passive transmission line (PTL) layers in the middle, and a DC power layer at the bottom. We describe the process conditions and the fabrication equipment. We use both diagnostic chips and shift register (SR) chips to improve the fabrication process. The diagnostic chip was designed to evaluate the characteristics of basic elements such as junctions, contacts, resisters, and wiring, in addition to their defect evaluations. The SR chip was designed to evaluate defects depending on the size of the SFQ circuits. The results of a long-term evaluation of the diagnostic and SR chips showed that there was fairly good correlation between the defects of the diagnostic chips and yields of the SRs. We could obtain a yield of 100% for SRs including 70,000JJs. These results show that considerable progress has been made in reducing the number of defects and improving reliability.
To improve circuit density and minimize static power dissipation in Single Flux Quantum (SFQ) circuits, this work investigates the application of inductively biased, unshunted Josephson transmission lines (JTLs) which achieve zero static power, compared with regular resistively biased JTLs. Both simulation and experiment results confirm that unshunted JTLs can reliably propagate SFQ pulses with a bias current margin larger than 50%. Based on this, a new fabrication process has been developed featuring eight niobium (Nb) layers, including two Nb/Al-AlOx/Nb junction layers, a dedicated bias-inductor layer, and dual DC-power layers. The vertical functional separation allows 2 active layers. The 1stactive layer uses conventional shunted JJs for logic gates, while the 2nduses unshunted JTLs with inductive bias. This configuration eliminates static power in the interconnect network and simplifies thermal management in stacked Rapid SFQ (RSFQ) architectures. A ten-stage unshunted JTL chain and a hybrid half-adder were designed and demonstrated. Measurements show a 66.7% reduction in static power and a 64.7% reduction in area compared with the Chinese Academy of Scienceconventional single-JJ-layer process. These results verify, for the first time, that inductively biased unshunted interconnects can be monolithically integrated with standard RSFQ logic, offering a scalable path toward ultra-dense, lower-power multilayer superconducting circuits.
The increase in the single-flux-quantum (SFQ) circuit scale will cause the overall bias current to increase dramatically. The magnetic field interference caused by the current supplied to the SFQ circuit can no longer be ignored. In addition, more complex SFQ circuits require a cell library for more diversified cell types and a more stable operating range to ensure the circuits’ yield. The SIMIT-Nb03P process is then put forward as a tradeoff between process stability and cost. It is compatible with the Nb03 process and does not need an expensive chemical mechanical planarization process. The added new dc power layer is proved to have less interference by simulation. The conversion from Nb03 to Nb03P cell library was very convenient. In addition, some new cells are designed to meet the requirements of complex SFQ circuits. Test circuits of 20 cells of Nb03P were designed and fabricated and were fully verified at low frequencies. The common bias margin of the whole cell library is (–26%, 20%). A variety of large-scale circuits (up to more than 10 000 Josephson junctions) achieve correct function at high frequencies and show good yields on the wafer. It shows that this updated process is cost efficient and suitable for large-scale integration circuits.