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IEEE Conference on Electrical Performance of Electronic Packaging and Systems (EPEPS)

Superconducting sampling measurement system for characterization of electronic packaging

Masahiro Aoyagi, Hiroshi Sato, Hiroshi Nakagawa, Hiroshi Akoh, Hannes Toepfer

Published Nov 11, 2002• 1 citation
Publisher

Abstract

A superconducting sampling measurement system is a highly useful tool for analyzing ultrahigh speed electrical signals in cryogenic environments, due to a time resolution at ps levels with low current levels of /spl mu/A. The digitizing sampling system is composed of a Josephson sampling circuit, digital delay line, feedback signal detection circuit and a computer. The Josephson sampling circuit is designed for ETL's Nb-AlO/sub x/-Nb junction technology. A TDR measurement method using a CPW flip-chip bonding technique is proposed. The theoretical spatial resolution is estimated to reach around a hundred /spl mu/m.

DOI
10.1109/epep.2000.895512

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A superconducting sampling measurement system is a highly useful tool for analyzing ultrahigh speed electrical signals in cryogenic environments, due to a time resolution at ps levels with low current levels of /spl mu/A. The digitizing sampling system is composed of a Josephson sampling circuit, digital delay line, feedback signal detection circuit and a computer. The Josephson sampling circuit is designed for ETL's Nb-AlO/sub x/-Nb junction technology. A TDR measurement method using a CPW flip-chip bonding technique is proposed. The theoretical spatial resolution is estimated to reach around a hundred /spl mu/m.
HYPRES, Inc. has introduced to the commercial marketplace a Sampling Oscilloscope/Time Domain Reflectometer (TDR) based on Josephson junction technology. The unit offers measurement performance commensurate with the inherent high speed of the Josephson elements, e.g., bandwidths in excess of 70 GHz and rise times on the order of 5 ps. A Josephson {rigger recognizer and delay circuit allows triggering of the sampling oscilloscope from the signal itself, with full view of the trigger point. Input modules offering different sensitivities or TDR capability are quickly interchangeable, and operating temperature is achieved in less than one minute. The technical details of the cooling technique and the chip circuitry will be described in this paper .
The authors propose a new type of sampler design based on shunted junctions ( beta c =1). The sampler is to be used for the investigation of single flux quantum devices (RSFQ) employing similar junctions (Kaplunenko et al. 1989, Filippenko et al. 1991). They measure the time resolution of the sampler and delay time of the shunted Josephson junction array. The circuit was manufactured on a single chip and was DC powered. They employed Nb-AlO x -Nb tunnel junctions of 300 A m -2 critical current density and observed Josephson oscillations of the output junction at frequencies from 6 to 50 GHz. Despite a long plasma period of 20 ps the time resolution was 5 ps. The transmission line of 27 Josephson junctions (critical current 165 mu A each) demonstrated time delay of 0.5 ps mu A -1 .
Measurement of signals generated by superconducting Josephson junction (JJ) circuits require ultra-fast components located in close proximity to the generating circuitry. We report a detailed study of optimal design criteria for a JJ-based sampler which balances the highest sampler bandwidth (shortest 10\%--90\% rise time) with minimal sampled waveform distortion. We explore the impacts on performance of a sampler, realized using a single underdamped JJ as the logical sampling element (the comparator), due to the type of signal-comparator coupling scheme that is utilized (galvanic, inductive, or capacitive). In these simulations we emulate the entire waveform reconstruction sampling process, via comparator threshold detection, while sweeping the time location at which the waveform is being sampled. We extract the sampled waveform rise time (or FWHM) as a function of the comparator's Stewart-McCumber parameter and as a function of the coupling strength between the device under test and comparator. Based on our simulation results we design, fabricate, and characterize a cryocooled (3.6 K operating temperature) JJ sampler utilizing the NIST state-of-the-art Nb/amorphous-Si/Nb junctions. We separately sample a step signal and impulse generator co-located on-chip with the comparator and sampling strobe generator by implementing the same binary search comparator threshold detection technique during sampler operation as is used in simulation. With this technique the system is fully-digital and automated and operation of the fabricated device directly mirrors simulation. Our sampler technology shows a 10\%--90\% rise time of 3.3 ps and the capability to measure transient pulse widths of 2.5 ps FWHM. A linear systems analysis of sampled waveforms indicate a 3 dB bandwidth of 225 GHz, but we demonstrate effective measurement of signals well above this -- as high as 600 GHz.
Measurement of signals generated by superconducting Josephson junction (JJ) circuits require ultra-fast components located in close proximity to the generating circuitry. We report a detailed study of optimal design criteria for a JJ-based sampler that balances the highest sampler bandwidth (shortest 10%-90% rise time) with minimal sampled waveform distortion. We explore the impacts on the performance of a sampler, realized using a single underdamped JJ as the logical sampling element (the comparator), due to the type of signal-comparator coupling scheme that is utilized (galvanic, inductive, or capacitive). In these simulations, we emulate the entire waveform reconstruction sampling process, via comparator threshold detection, while sweeping the time location at which the waveform is being sampled. We extract the sampled waveform rise time [or full width at half maximum (FWHM)] as a function of the comparator's Stewart-McCumber parameter and as a function of the coupling strength between the device under test and comparator. Based on our simulation results, we design, fabricate, and characterize a cryocooled (3.6 K operating temperature) JJ sampler utilizing the NIST state-of-the-art Nb/amorphous-Si/Nb junctions. We separately sample a step signal and an impulse generator co-located on-chip with the comparator and sampling strobe generator by implementing the same binary search comparator threshold detection technique during sampler operation as is used in simulation. With this technique, the system is fully digital and automated, and the operation of the fabricated device directly mirrors simulation. Our sampler technology shows a 10%-90% rise time of 3.3 ps and the capability to measure transient pulse widths of 2.5 ps FWHM. A linear system analysis of sampled waveforms indicates a 3 dB bandwidth of 225 GHz, but we demonstrate effective measurement of signals well above this-as high as 600 GHz.
HYPRES, Inc. has introduced a Sampling Oscilloscope/Time Domain Reflectometer (TDR) based on Josephson junction technology to the commercial marketplace. The unit offers measurement performance commensurate with the inherent high speed of the Josephson elements, e.g., risetimes on the order of 8 ps. The Josephson circuitry is contained on a single 1.1 × 1.6 fused silica substrate and housed in an interchangeable measurement module. Only the portion of the chip which contains the superconducting circuitry is cooled with a coplanar transmission line providing the wide bandwidth interface between the room temperature and cryogenic environments less than 1cm apart.
We have investigated and tried to improve the packaging technologies for a bit-error-rate (BER) measurement system for high-T/sub c/ superconducting circuits. Signal cables, test fixture, and magnetic shields were specially designed and assembled for the BER measurement system, taking into account electrical losses, signal reflection, heat inflow, and power consumption of a cryocooler. BER was further improved by changing the way of connection between the semiconductor amplifiers outside the sample vacuum chamber. These improvements led to a BER less than 10/sup -12/ at an output voltage (V/sub out/) of 1.7 and 2.3 mV for a 50-/spl Omega/ standard microstrip transmission line and a superconducting microstrip-line to coplanar-waveguide transmission-line converter, respectively. The temperature rise of the test fixture was as low as about 2 K. These values are approximately one order of magnitude smaller than those in the previous measurement system and small enough to be achieved by using superconducting interface circuits. Furthermore, 1-Gb/s operation of a superconducting quantum interference device array-type interface circuit was demonstrated in the BER measurement system at 40 K.