This paper proposes a VHDL-based simulation technique for studying the effects of noise on fault tolerant quantum circuits using fault injection. We aimed at an accurate fault modeling using a Hardware Description Language CAD environment that yields relevant results. However, the resources needed for simulated fault injection become prohibitive with the growth of the circuit (i.e. for the worst case simulation resources grow exponentially with the number of qubits). Furthermore, the fault tolerant mechanisms rely on quantum error correction codes and concatenated coding that further increase the complexity of the analyzed circuit. We address these problems, by proposing a multi-phase approach, based on a two-phase simulation for assessing fault tolerance. In the first phase, the basic blocks of the encoded circuit are analyzed with the simulated fault injection methodology, yielding the noise parameters needed during the second phase, when the logical circuit is analyzed. We show that this approach yields a good approximation for noise values lower than 10−2.
This paper proposes a VHDL-based simulation technique for studying the effects of noise on fault tolerant quantum circuits using fault injection. We aimed at an accurate fault modeling using a Hardware Description Language CAD environment that yields relevant results. However, the resources needed for simulated fault injection become prohibitive with the growth of the circuit (i.e. for the worst case simulation resources grow exponentially with the number of qubits). Furthermore, the fault tolerant mechanisms rely on quantum error correction codes and concatenated coding that further increase the complexity of the analyzed circuit. We address these problems, by proposing a multi-phase approach, based on a two-phase simulation for assessing fault tolerance. In the first phase, the basic blocks of the encoded circuit are analyzed with the simulated fault injection methodology, yielding the noise parameters needed during the second phase, when the logical circuit is analyzed. We show that this approach yields a good approximation for noise values lower than 10−2.
This paper presents a flexible VHDL simulation framework, meant to analyze the link between the adopted noise model and the quantum circuit fidelity. The key ingredient is the use of fault injection components (i.e. mutants and saboteurs), which are tailored according to the noise model. The evaluation of quantum fault tolerant (FT) schemes is dominated by analytical studies, mostly restricted to independent probabilistic faults. The model adopted herein addresses general noise, which includes: probabilistic faults, amplitude errors, depolarization, amplitude damping, and phase damping. This way, we show that a rigorous CAD analysis for lower levels of FT schemes can be performed. The results can then be used to tune up simulation or analytical parameters for the higher levels. The target of our simulations is a particular quantum network, responsible for generating and verifying the encoded ancilla state |0rangF.
Quantum error correction codes are essential for fault-tolerant quantum computing. They are a method of detecting and correcting errors in a quantum computer by encoding logical qubits across multiple physical qubits. Several prominent error correction codes have been developed and larger and more complex codes are being developed continuously. However, evaluating the fault-tolerance of these larger codes is becoming exponentially more complicated. While conventional methods of proving and evaluating the fault-tolerance of these circuits have worked thus far, they are soon to be obsolete. The aim of this thesis is to develop a framework that automatically evaluates the fault-tolerance of a quantum error correction circuit across different hardware architectures. The framework works as follows: it takes a noiseless quantum error correction code; injects hardware-realistic noise into it; and evaluates the fault-tolerance of the resulting noisy circuit by estimating its logical error rate through Monte Carlo sampling. For the injection of hardware-realistic noise, this thesis considers noise stemming from five different quantum computing hardware architectures: superconducting qubits, neutral atoms, trapped ions, photonic qubits, and spin qubits. The noise model was constructed by extracting single-qubit gate, two-qubit gate and measurement error fidelities from current experimental literature. The noise model and circuit generation is implemented in Python, circuit representation and noise injection is executed in Stim and decoding and estimating the logical error rate is achieved through PyMatching. The framework is evaluated on the repetition code, the surface code, and the color code; the logical error rate is estimated across all five hardware architectures under the noise model; and the results are discussed in the context of hardware compatibility for the given codes.
This report aims at presenting the research program and to review the literature describing quantum computing, quantum fault tolerance issues and classical fault injection. Thus, previous work is presented together with future research directions. The proposed PhD research program aims at developing a methodology for simulation based fault injection for quantum circuits. Through simulation, I obtain a statistically significant sample in order to provide a quantitative means to assess quantum circuit reliability. A desired feature of the fault injection methodology is scalability. Nevertheless, quantum circuit simulation requires simulation resources that grow exponentially with the number of simulated qubits. Although, simulation techniques that improve the simulation cost and/or time were developed, still for complex and large structures it is not feasible to apply fault injection. In order to overcome this obstacle and obtain scalability, I propose a logic partitioning. The complex and large quantum circuit is decomposed into less complex parts. Fault injection is used to evaluate quantum reliability for these parts. The reliability for
This paper addresses the problem of evaluating the Fault Tolerance Algorithms and Methodologies (FTAMs) for quantum circuits, by making use of fault injection techniques. The proposed mutant-based fault injection techniques are inspired from their classical counterparts [3][8], and were adapted to the specific features of quantum computation, including the available error models [4][5]. The HDLs were employed in order to perform fault injection, due to their capacity of behavioral and structural circuit description, as well as their hierarchical features. Besides providing a much realistic description, the experimental simulated fault injection campaigns provide quantitative means for quantum fault tolerance assessment.
This paper addresses the problem of evaluating the fault tolerance algorithms and methodologies (FTAMS) designed for quantum circuits, by making use of fault injection techniques. These techniques are inspired from their rich classical counterparts, and were adapted to the quantum computation specific features, including the available error models. Because of their wide spectrum of application, including quantum circuit simulation, and their flexibility in circuit representation (i.e. both behavioral and structural descriptions of a circuit are possible), the hardware description languages (HDLs) appear as the best choice for our simulation experiments. The techniques employed for fault injection are based on simulator commands. The simulation results for the fault-affected circuit were compared to the outputs of a Gold circuit (a faultless circuit) in order to compute the quantum failure rate.
This thesis is concerned with certain theoretical problems that arise naturally in the context of fault-tolerant quantum computation. Fault-tolerance can be defined as the art of building reliable devices from unreliable components, and is of particular importance for quantum computers that aim to precisely control the dynamics of extremely sensitive quantum systems. A model of quantum computation is a specification of the basic building blocks by which a quantum computation is implemented. The best known model is the quantum circuit model, where computations are implemented by means of unitary quantum gates that are applied to two-level quantum systems known as qubits. In a physical implementation of a quantum circuit, the gates and qubits will inevitably be affected by noise. Fault-tolerant quantum circuits are designed to be resilient against the effects of this noise, provided that it is not too strong. Fault-tolerance in the quantum circuit model is well developed thanks to the theory of quantum error-correcting codes. These codes allow for the correction of small numbers of errors introduced by a variety of noise processes. In a fault-tolerant quantum circuit, qubits are replaced with encoded qubits, and quantum gates with encoded gates that are immediately followed by special quantum circuits for error correction. Provided the rate at which errors occur is below a constant threshold value, the accumulation of errors can be checked so that the correct output of the computation correctly determined. The threshold acts as both a measure of how good the design of a quantum circuit is, and also as a target for experimenters aiming to implement quantum circuits. Much current research in quantum computation is aimed at designing quantum circuits that increase the noise threshold, hopefully to the point where it becomes within the reach of experimenters. A fault-tolerant encoded quantum gate must limit the propagation of errors so that the code’s corrective capabilities are not overwhelmed. It is not so easy to design encoded gates that satisfy this property, and to date only a finite handful of such gates are known. In a faulttolerant quantum circuit, all quantum gates must be decomposed or compiled in terms of those that may be implemented fault-tolerantly. In the first part of this thesis, we present two results that may be applied to this problem of gate compilation. The first is a generic method based on the Solovay-Kitaev theorem that may be applied to all quantum gates, but is most effective for those that act on single qubits. We present the Solovay-Kitaev theorem in its simples known form as an algorithm, together with novel constructions that can be used to implement it. Following this we give a two specialized methods for two-qubit gate decomposition, based on the Cartan decomposition of the Lie group SU(4). The cluster-state model of computation is an alternative to the quantum circuit model, and makes use of quantum measurements and highly entangled cluster-states to implement a quantum computation. The fault-tolerant techniques developed for quantum circuits are not immediately applicable in this model, so in order for it to be a realistic candidate for performing computations we prove that such techniques are possible. In the second part of the thesis we prove that constant fault-tolerance thresholds may be achieved in the cluster-state model, and in particular in an adaption to an optical implementation. Following this we design a complete error correction scheme for optical cluster-state computation, and numerically determine the threshold of this model in the face of the dominant noise models likely to affect such an implementation.