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Simulation-Based Assessment of Quantum Circuit Reliability

Oana Boncalo

Published Jan 1, 2007• 0 citations

Abstract

This report aims at presenting the research program and to review the literature describing quantum computing, quantum fault tolerance issues and classical fault injection. Thus, previous work is presented together with future research directions. The proposed PhD research program aims at developing a methodology for simulation based fault injection for quantum circuits. Through simulation, I obtain a statistically significant sample in order to provide a quantitative means to assess quantum circuit reliability. A desired feature of the fault injection methodology is scalability. Nevertheless, quantum circuit simulation requires simulation resources that grow exponentially with the number of simulated qubits. Although, simulation techniques that improve the simulation cost and/or time were developed, still for complex and large structures it is not feasible to apply fault injection. In order to overcome this obstacle and obtain scalability, I propose a logic partitioning. The complex and large quantum circuit is decomposed into less complex parts. Fault injection is used to evaluate quantum reliability for these parts. The reliability for

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This report aims at presenting the research program and to review the literature describing quantum computing, quantum fault tolerance issues and classical fault injection. Thus, previous work is presented together with future research directions. The proposed PhD research program aims at developing a methodology for simulation based fault injection for quantum circuits. Through simulation, I obtain a statistically significant sample in order to provide a quantitative means to assess quantum circuit reliability. A desired feature of the fault injection methodology is scalability. Nevertheless, quantum circuit simulation requires simulation resources that grow exponentially with the number of simulated qubits. Although, simulation techniques that improve the simulation cost and/or time were developed, still for complex and large structures it is not feasible to apply fault injection. In order to overcome this obstacle and obtain scalability, I propose a logic partitioning. The complex and large quantum circuit is decomposed into less complex parts. Fault injection is used to evaluate quantum reliability for these parts. The reliability for

This paper addresses the problem of evaluating the Fault Tolerance Algorithms and Methodologies (FTAMs) for quantum circuits, by making use of fault injection techniques. The proposed mutant-based fault injection techniques are inspired from their classical counterparts [3][8], and were adapted to the specific features of quantum computation, including the available error models [4][5]. The HDLs were employed in order to perform fault injection, due to their capacity of behavioral and structural circuit description, as well as their hierarchical features. Besides providing a much realistic description, the experimental simulated fault injection campaigns provide quantitative means for quantum fault tolerance assessment.

The importance of reliability and fault tolerance is paramount in quantum computation. This paper proposes a Fault Tolerance Algorithms and Methodologies (FTAM) assessment technique for quantum circuits, by adopting the saboteur-based Simulated Fault Injection methodology from classical computation. By drawing the inspiration from classical computation, the HDLs were employed for performing fault injection, due to their capacity of behavioral and structural circuit description, including hierarchical features. The cornerstone of this approach is the adaptation of the available quantum computation error models (with the quantum computing features and constraints) to the classical, HDL framework of the simulated fault injection techniques. The experimental simulated fault injection campaign results are consistent with the analytical assessments -from a qualitative point of view - but at the same time they provide a much realistic description.

The importance of reliability and fault tolerance is paramount in quantum computation. This paper proposes a Fault Tolerance Algorithms and Methodologies (FTAM) assessment technique for quantum circuits, by adopting the saboteur-based Simulated Fault Injection methodology from classical computation. By drawing the inspiration from classical computation, the HDLs were employed for performing fault injection, due to their capacity of behavioral and structural circuit description, including hierarchical features. The cornerstone of this approach is the adaptation of the available quantum computation error models (with the quantum computing features and constraints) to the classical, HDL framework of the simulated fault injection techniques. The experimental simulated fault injection campaign results are consistent with the analytical assessments -from a qualitative point of view - but at the same time they provide a much realistic description.

This paper addresses the problem of evaluating the Fault Tolerance Algorithms and Methodologies (FTAMs) designed for quantum systems, by adopting the Simulated Fault Injection methodology from classical computation. Due to their wide spectrum of applications (including quantum circuit simulation) and hierarchical features, the HDLs were employed for performing fault injection, as prescribed by the guidelines of the QUERIST project. At the same time, the injection techniques taken from classical circuit simulation had to be adapted to quantum computation requirements, including the specific quantum error models. The experimental simulated fault injection campaigns are thoroughly described along with the experimental results, which confirm the analytical expectations.

This paper addresses the problem of evaluating the fault tolerance algorithms and methodologies (FTAMS) designed for quantum circuits, by making use of fault injection techniques. These techniques are inspired from their rich classical counterparts, and were adapted to the quantum computation specific features, including the available error models. Because of their wide spectrum of application, including quantum circuit simulation, and their flexibility in circuit representation (i.e. both behavioral and structural descriptions of a circuit are possible), the hardware description languages (HDLs) appear as the best choice for our simulation experiments. The techniques employed for fault injection are based on simulator commands. The simulation results for the fault-affected circuit were compared to the outputs of a Gold circuit (a faultless circuit) in order to compute the quantum failure rate.

Quantum error correction codes are essential for fault-tolerant quantum computing. They are a method of detecting and correcting errors in a quantum computer by encoding logical qubits across multiple physical qubits. Several prominent error correction codes have been developed and larger and more complex codes are being developed continuously. However, evaluating the fault-tolerance of these larger codes is becoming exponentially more complicated. While conventional methods of proving and evaluating the fault-tolerance of these circuits have worked thus far, they are soon to be obsolete. The aim of this thesis is to develop a framework that automatically evaluates the fault-tolerance of a quantum error correction circuit across different hardware architectures. The framework works as follows: it takes a noiseless quantum error correction code; injects hardware-realistic noise into it; and evaluates the fault-tolerance of the resulting noisy circuit by estimating its logical error rate through Monte Carlo sampling. For the injection of hardware-realistic noise, this thesis considers noise stemming from five different quantum computing hardware architectures: superconducting qubits, neutral atoms, trapped ions, photonic qubits, and spin qubits. The noise model was constructed by extracting single-qubit gate, two-qubit gate and measurement error fidelities from current experimental literature. The noise model and circuit generation is implemented in Python, circuit representation and noise injection is executed in Stim and decoding and estimating the logical error rate is achieved through PyMatching. The framework is evaluated on the repetition code, the surface code, and the color code; the logical error rate is estimated across all five hardware architectures under the noise model; and the results are discussed in the context of hardware compatibility for the given codes.