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European Conference on Circuit Theory and Design

Assessing quantum circuits reliability with mutant-based simulated fault injection

Oana Boncalo, Mihai Udrescu, Lucian Prodan, Mircea Vlăduţiu, Alexandru Amaricăi

Published Aug 1, 2007• 4 citations
Publisher

Abstract

This paper addresses the problem of evaluating the Fault Tolerance Algorithms and Methodologies (FTAMs) for quantum circuits, by making use of fault injection techniques. The proposed mutant-based fault injection techniques are inspired from their classical counterparts [3][8], and were adapted to the specific features of quantum computation, including the available error models [4][5]. The HDLs were employed in order to perform fault injection, due to their capacity of behavioral and structural circuit description, as well as their hierarchical features. Besides providing a much realistic description, the experimental simulated fault injection campaigns provide quantitative means for quantum fault tolerance assessment.

DOI
10.1109/ecctd.2007.4529753

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This paper addresses the problem of evaluating the Fault Tolerance Algorithms and Methodologies (FTAMs) for quantum circuits, by making use of fault injection techniques. The proposed mutant-based fault injection techniques are inspired from their classical counterparts [3][8], and were adapted to the specific features of quantum computation, including the available error models [4][5]. The HDLs were employed in order to perform fault injection, due to their capacity of behavioral and structural circuit description, as well as their hierarchical features. Besides providing a much realistic description, the experimental simulated fault injection campaigns provide quantitative means for quantum fault tolerance assessment.
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The importance of reliability and fault tolerance is paramount in quantum computation. This paper proposes a Fault Tolerance Algorithms and Methodologies (FTAM) assessment technique for quantum circuits, by adopting the saboteur-based Simulated Fault Injection methodology from classical computation. By drawing the inspiration from classical computation, the HDLs were employed for performing fault injection, due to their capacity of behavioral and structural circuit description, including hierarchical features. The cornerstone of this approach is the adaptation of the available quantum computation error models (with the quantum computing features and constraints) to the classical, HDL framework of the simulated fault injection techniques. The experimental simulated fault injection campaign results are consistent with the analytical assessments -from a qualitative point of view - but at the same time they provide a much realistic description.
The importance of reliability and fault tolerance is paramount in quantum computation. This paper proposes a Fault Tolerance Algorithms and Methodologies (FTAM) assessment technique for quantum circuits, by adopting the saboteur-based Simulated Fault Injection methodology from classical computation. By drawing the inspiration from classical computation, the HDLs were employed for performing fault injection, due to their capacity of behavioral and structural circuit description, including hierarchical features. The cornerstone of this approach is the adaptation of the available quantum computation error models (with the quantum computing features and constraints) to the classical, HDL framework of the simulated fault injection techniques. The experimental simulated fault injection campaign results are consistent with the analytical assessments -from a qualitative point of view - but at the same time they provide a much realistic description.
This paper addresses the problem of evaluating the fault tolerance algorithms and methodologies (FTAMS) designed for quantum circuits, by making use of fault injection techniques. These techniques are inspired from their rich classical counterparts, and were adapted to the quantum computation specific features, including the available error models. Because of their wide spectrum of application, including quantum circuit simulation, and their flexibility in circuit representation (i.e. both behavioral and structural descriptions of a circuit are possible), the hardware description languages (HDLs) appear as the best choice for our simulation experiments. The techniques employed for fault injection are based on simulator commands. The simulation results for the fault-affected circuit were compared to the outputs of a Gold circuit (a faultless circuit) in order to compute the quantum failure rate.
This report aims at presenting the research program and to review the literature describing quantum computing, quantum fault tolerance issues and classical fault injection. Thus, previous work is presented together with future research directions. The proposed PhD research program aims at developing a methodology for simulation based fault injection for quantum circuits. Through simulation, I obtain a statistically significant sample in order to provide a quantitative means to assess quantum circuit reliability. A desired feature of the fault injection methodology is scalability. Nevertheless, quantum circuit simulation requires simulation resources that grow exponentially with the number of simulated qubits. Although, simulation techniques that improve the simulation cost and/or time were developed, still for complex and large structures it is not feasible to apply fault injection. In order to overcome this obstacle and obtain scalability, I propose a logic partitioning. The complex and large quantum circuit is decomposed into less complex parts. Fault injection is used to evaluate quantum reliability for these parts. The reliability for
This paper proposes a VHDL-based simulation technique for studying the effects of noise on fault tolerant quantum circuits using fault injection. We aimed at an accurate fault modeling using a Hardware Description Language CAD environment that yields relevant results. However, the resources needed for simulated fault injection become prohibitive with the growth of the circuit (i.e. for the worst case simulation resources grow exponentially with the number of qubits). Furthermore, the fault tolerant mechanisms rely on quantum error correction codes and concatenated coding that further increase the complexity of the analyzed circuit. We address these problems, by proposing a multi-phase approach, based on a two-phase simulation for assessing fault tolerance. In the first phase, the basic blocks of the encoded circuit are analyzed with the simulated fault injection methodology, yielding the noise parameters needed during the second phase, when the logical circuit is analyzed. We show that this approach yields a good approximation for noise values lower than 10−2.