Quantum error correction codes are essential for fault-tolerant quantum computing. They are a method of detecting and correcting errors in a quantum computer by encoding logical qubits across multiple physical qubits. Several prominent error correction codes have been developed and larger and more complex codes are being developed continuously. However, evaluating the fault-tolerance of these larger codes is becoming exponentially more complicated. While conventional methods of proving and evaluating the fault-tolerance of these circuits have worked thus far, they are soon to be obsolete. The aim of this thesis is to develop a framework that automatically evaluates the fault-tolerance of a quantum error correction circuit across different hardware architectures. The framework works as follows: it takes a noiseless quantum error correction code; injects hardware-realistic noise into it; and evaluates the fault-tolerance of the resulting noisy circuit by estimating its logical error rate through Monte Carlo sampling. For the injection of hardware-realistic noise, this thesis considers noise stemming from five different quantum computing hardware architectures: superconducting qubits, neutral atoms, trapped ions, photonic qubits, and spin qubits. The noise model was constructed by extracting single-qubit gate, two-qubit gate and measurement error fidelities from current experimental literature. The noise model and circuit generation is implemented in Python, circuit representation and noise injection is executed in Stim and decoding and estimating the logical error rate is achieved through PyMatching. The framework is evaluated on the repetition code, the surface code, and the color code; the logical error rate is estimated across all five hardware architectures under the noise model; and the results are discussed in the context of hardware compatibility for the given codes.
Quantum error correction codes are essential for fault-tolerant quantum computing. They are a method of detecting and correcting errors in a quantum computer by encoding logical qubits across multiple physical qubits. Several prominent error correction codes have been developed and larger and more complex codes are being developed continuously. However, evaluating the fault-tolerance of these larger codes is becoming exponentially more complicated. While conventional methods of proving and evaluating the fault-tolerance of these circuits have worked thus far, they are soon to be obsolete. The aim of this thesis is to develop a framework that automatically evaluates the fault-tolerance of a quantum error correction circuit across different hardware architectures. The framework works as follows: it takes a noiseless quantum error correction code; injects hardware-realistic noise into it; and evaluates the fault-tolerance of the resulting noisy circuit by estimating its logical error rate through Monte Carlo sampling. For the injection of hardware-realistic noise, this thesis considers noise stemming from five different quantum computing hardware architectures: superconducting qubits, neutral atoms, trapped ions, photonic qubits, and spin qubits. The noise model was constructed by extracting single-qubit gate, two-qubit gate and measurement error fidelities from current experimental literature. The noise model and circuit generation is implemented in Python, circuit representation and noise injection is executed in Stim and decoding and estimating the logical error rate is achieved through PyMatching. The framework is evaluated on the repetition code, the surface code, and the color code; the logical error rate is estimated across all five hardware architectures under the noise model; and the results are discussed in the context of hardware compatibility for the given codes.
Quantum computers promise to solve computational problems that are inaccessible to classical machines. The reliable execution of large-scale quantum algorithms requires robust operations in the presence of noise. Quantum error correction addresses this challenge by encoding quantum information redundantly across several physical qubits, such that errors can be detected and corrected during a computation. However, no single error-correcting code intrinsically supports an inherently robust, fault-tolerant implementation of all gates needed for universal quantum computing. Moreover, most modern approaches to both quantum error correction and the implementation of universal logical operations on encoded qubits rely on mid-circuit measurements and feed-forward control. These types of operations are technologically demanding, often slow, and prone to high error rates, and they limit the overall success probability of quantum algorithms. In this thesis, we develop fault-tolerant protocols and circuits for quantum error correction and universal logical computation, with an emphasis on implementations compatible with current hardware systems. We first focus on fault-tolerant quantum error correction on small codes. By comparing different protocols, we identify trade-offs between compact circuit constructions and their robustness to noise. We then assess their practical performance by comparing numerical simulations of noisy circuits with experimental data. Beyond the preservation of encoded information, we study how universal logic can be implemented in a fault-tolerant manner on encoded qubits. A central approach considered in this thesis is code switching, in which logical information is transferred between two distinct error-correcting codes that support complementary sets of inherently fault-tolerant logical gates. In combination, these codes give access to a complete universal fault-tolerant logical gate set. In this thesis, we determine conditions that allow us to construct fault-tolerant protocols for code switching. We adapt these protocols to the capabilities of current hardware, thereby enabling the first experimental realization of universal fault-tolerant logic by means of code switching. However, the overall performance of these schemes is limited by slow and noisy mid-circuit measurements. To address this bottleneck, we construct a suite of measurement-free fault-tolerant universal operations that do not require any measurements during the execution of an algorithm. In this framework, error correction and logical operations are implemented coherently as part of the quantum circuit, without mid-circuit measurements or in-sequence classical control. We introduce measurement-free code-switching schemes that can be scaled to arbitrary code distances through concatenation, and which thereby provide, in principle, arbitrarily strong error suppression. We further tailor our approach to the capabilities of current trapped-ion quantum processors. New circuit constructions support the first experimental implementation of a logical quantum algorithm without mid-circuit measurements, demonstrated through Grover's search on three encoded qubits. Together, the results of this thesis expand the toolbox for early fault-tolerant quantum computation. They show how protocols for quantum error correction and universal logical gates can be designed without mid-circuit measurements with realistic hardware constraints in mind, opening new pathways towards universal quantum logic.
Quantum computing has reached a pivotal inflection point with the recent demonstration ofbelow-threshold quantum error correction and the emergence of logical qubits that outperformtheir physical counterparts. This review synthesizes the remarkable progress achieved between2024 and 2026 across multiple quantum hardware platforms, including superconducting circuits,trapped ions, and neutral atom arrays. We examine the theoretical foundations of quantumerror correction codes, with particular emphasis on surface codes and the rapidly advancingquantum low-density parity-check (qLDPC) codes. Key experimental milestones are analyzed,including Google’s Willow chip demonstration of exponential error suppression, IBM’s modularfault-tolerant roadmap culminating in the Starling system, IonQ’s achievement of 48 logicalqubits with a 2:1 encoding ratio, and QuEra’s record-efficiency neutral atom error correctionapproaching the Teraquop regime. The review further explores critical enabling technologiessuch as real-time decoding architectures, magic state distillation protocols, and fault-tolerant gateimplementations. We discuss the remaining challenges in scaling to hundreds of logical qubits,achieving practical logical error rates of 10−10 to 10−15, and realizing end-to-end fault-tolerantalgorithms. By synthesizing these developments, this article provides a comprehensive assessmentof the field’s trajectory toward practical fault-tolerant quantum computing and identifies the keymilestones that will define the next phase of progress.
Quantum computation holds the promise of solving certain complex problems exponentially faster than classical computers. However, the high prevalent noise in current quantum devices impedes the accurate execution of even basic algorithms. This can be remedied by protecting quantum information with a quantum error-correcting code, where the logical information of an algorithmic qubit is spread across multiple physical qubits. Individual quantum errors are then located and corrected by the fault-tolerant measurement of multi-qubit stabilizer operators (parity checks). Unfortunately, error correction and fault tolerance both impose large demands on the qubit overhead: hundreds to thousands of physical qubits per logical qubit.
We reduce the spacetime cost of fault tolerance by redesigning key building blocks of an error-corrected quantum computer. First, we develop a combinatorial proof with flag fault tolerance that exponentially reduces the extra qubits needed to measure a stabilizer of any size, while tolerating one fault. We leverage these proofs to then design state preparation circuits for the Steane and Golay codes with 100% yield. Next, we improve error correction on a planar layout by showing that a distance-four code encoding six logical qubits protects information as well as the distance-five surface code, using one-tenth as many physical qubits. Finally, we optimize the time overhead of logical gates in surface code quantum computers by protecting measurement results with a classical code, cutting computation time by a factor of two to six. Our hardware-agnostic optimizations of fault tolerance overheads thus suggest new routes to advance the timeline of error-free quantum computing.
Noise is the fundamental challenge to quantum computation. Large-scale quantum computers will overcome this challenge with fault-tolerant architectures that leverage quantum error correction. This thesis introduces and investigates a scalable noise characterisation protocol suited to this key context. First, we introduce this protocol by building upon averaged circuit eigenvalue sampling (ACES), a framework for noise characterisation experiments that simultaneously estimates the Pauli error probabilities of all gates in a Clifford circuit and captures averaged spatial correlations between gates implemented simultaneously in the layers of the circuit. We demonstrate the scalability and performance of our protocol through circuit-level numerical simulations of the entire noise characterisation procedure. Then we demonstrate in circuit-level numerical simulation that this protocol is practically capable of calibrating a fast correlated matching decoder, enabling noise-aware decoding. We find that noise-aware decoding increases the error suppression factor of the code, leading to reductions in the logical error rate that increase exponentially with the code distance. Finally, we present several results obtained from experimentally implementing this protocol. We use the noise characterisation results to design an improved syndrome extraction circuit for a heavy hexagon memory that is adapted to the noise characteristics of the quantum device. The model error of our noise characterisation results suggests that the circuit-level Pauli noise model estimated by ACES can describe the essential features of quantum noise. We also operate a heavy hexagon memory and use noise estimates to predict performance and inform decoding. These results demonstrate that Pauli noise estimates can calibrate decoders to enable noise-aware decoding and inform the co-design of quantum error correcting codes, decoders, fault-tolerant circuits, and quantum devices.
Quantum error correction (QEC) enables reliable computation on noisy hardware by encoding logical information across many physical qubits and periodically measuring parities to detect errors. A decoder is the classical algorithm that uses these measurements to infer which error most likely occurred, so that the system can correct it. The decoder's accuracy-how rarely it makes the wrong guess-directly determines the scale of quantum computation that can be reliably executed. With a wealth of competing decoding algorithms, a QEC system designer needs reliable methods to evaluate them. Today, the dominant approach is to evaluate decoders using Monte Carlo simulation. However, simulation has several drawbacks such as requiring many samples to produce low variance estimates.
In this work, we develop a new systematic analysis for evaluating decoders. We introduce a novel formal semantics of a core language for QEC programs that captures the de facto standard Stim circuit format, providing a principled theoretical foundation for the emerging space of fault-tolerant quantum systems design. Given a QEC program and a decoder, our verifier can quantify both the decoder accuracy and the decoder robustness to drift in physical error rate. Our approach has two key components: (i) a structured search over the space of possible errors; and (ii) a constrained polynomial optimization kernel. A thorough empirical evaluation of our approach suggests that it can outperform simulation, especially in low error rate regimes, and that it can be deployed to quantify decoder robustness over an interval of physical error rates.
We construct the first known fault-tolerant scheme for injecting states into quantum error-correcting codes with constant space and time overhead. That is, we construct a family of constant-rate quantum error-correcting codes for which a set of bare physical qubits can be injected, i.e. fault-tolerantly encoded, into a code block. Similarly, a code state can be ejected, i.e. fault-tolerantly decoded, back into bare physical qubits. We show that these injection and ejection procedures succeed under circuit-level locally stochastic noise, while incurring just a small constant probability of corrupting each qubit, which is unavoidable for bare physical qubits. We also show how to perform fault-tolerant error correction and code-state preparation under locally stochastic noise. All of our gadgets can be implemented with constant quantum circuit depth (i.e. are single-shot), and with a number of physical qubits growing linearly with the number of logical qubits, assuming the ability to run polynomial-sized noiseless classical circuits on the side.
We construct our quantum codes by taking a high-dimensional hypergraph product of classical LDPC codes, which in turn are a simplified version of Spielman's linear-time encodable codes (STOC'95). As our resulting product codes are only resilient to physical errors occurring with non-uniform probabilities across qubits, we then show how to concatenate with inner codes of various sizes to obtain fault-tolerance against uniform noise.