Challenges
Datasets
Workspaces
Papers
Discussions
Leaderboard
Log inSign up
Challenges
Datasets
Workspaces
Papers
Discussions
Leaderboard
Blog
Job Board
Q3AS

© 2026 Aqora Quantum S.A.S.

TermsPrivacyLegal Notice

IEEE Journal of Solid-State Circuits

Experimental single flux quantum NDRO Josephson memory cell

W.H. Henkels, J. H. Greiner

Published Oct 1, 1979• 23 citations
Publisher

Abstract

Single flux quantum nondestructive readout (NDRO) Josephson memory cells which store an energy of only ~6/spl times/10/SUP -20/ J have been successfully fabricated and operated for the first time. Margin enhancement due to quantization, and low operating currents render this cell an attractive basis for a <1 ns access-time Josephson cache memory designed with a 2.5 /spl mu/m technology.

DOI
10.1109/jssc.1979.1051272

Related papers

High density NDRO SFQ Joshepson interferometer momory cell

H. Beha

A new Single Flux-Quantum (SFQ) Nondestructive Read-Out (NDRO) random-access asymmetric 2-Josephson-junction interferometer memory cell with only one control line has been investigated and designed. The binary information is stored in the cell nonvolatilely without a bias current. For random access, this is the first known interferometer memory cell without a diagonal line. Therefore, this NDRO SFQ memory cell leads intrinsically to smaller cell area and simpler decoder schemes. A cell design of only 52 lithographic squares is given to demonstrate the potential for high-density memory chips. Wide nominal read and write operating margins are obtained. The NDRO interferometer memory cell proposed is promising for use in a high-performance Josephson computer.

IEEE Transactions on Magnetics•Nov 1, 1981•2 citations

Fundamental criteria for the design of high-performance Josephson nondestructive readout random access memory cells and experimental confirmation

W.H. Henkels

Fundamental design criteria for Josephson nondestructive readout random access memory (NDRO RAM) cells are presented, within the context of an LSI array environment. Emphasis is placed upon principles which are relevant to high performance. The criteria are elucidated via a specific design which is simulated and then experimentally evaluated in a technology with a smallest critical dimension of 5 μm. The specific cell differs from previously tested Josephson NDRO cells in several respects; namely, the cell stores only ∼8Φ0, employs interferometer gates and an external damping resistor, allows switching into device resonances, and eliminates the need for a special initialization cycle. The cell-selection scheme, employing triple coincidence, results in larger operating margins and smaller operating currents than have previously been achieved. The large operating margins and all basic cell design criteria were experimentally verified. The experimental interferometer gate characteristics were analyzed in detail and found to be describable by simple models. In addition, it was discovered that single flux quantum transitions in the interferometer gates could be exploited beneficially in order to enhance the insensitivity of operating margins to fabrication tolerances.

Journal of Applied Physics•Dec 1, 1979•26 citations

Single flux-quantum Josephson memory cell using a new threshold characteristic

I. Kurosawa, Akihiko Yagi, Hiroshi Nakagawa +1 more

A new single flux-quantum Josephson memory cell in which nondestructive readout (NDRO) operations can be realized with a simple circuit configuration is proposed. The memory cell utilizes a new type of threshold characteristics in an equivalent asymmetric dc superconducting quantum interference device (SQUID) consisting of a three-junction SQUID gate and a single junction. NDRO operation has been successfully demonstrated in an experimental memory circuit.

Applied Physics Letters•Dec 1, 1983•11 citations

Experimental vortex transitional nondestructive read-out Josephson memory cell

Shuichi Tahara, Ichiro Ishida, Yumi Ajisawa +1 more

A proposal vortex transitional nondestructive read-out Josephson memory cell is successfully fabricated and tested. The memory cell consists of two superconducting loops in which a single flux quantum is stored and a two-junction interferometer gate as a sense gate. The memory cell employs vortex transitions in the superconducting loops for writing and reading data. The vortex transitional memory operation of the cell contributes to improving its sense discrimination and operating margin. The memory cell is activated by two control signals without timing control signals. Memory cell chips have been fabricated using a niobium planarization process. A±21% address signal current margin and a ±33% sense gate current margin have been obtained experimentally. Successful memory operations of a cell driven by two-junction interferometer gates has been demonstrated. The single flux quantum operations of this memory cell makes it an attractive basic element for a high-speed cache memory.

Journal of Applied Physics•Jan 15, 1989•42 citations

A Vortex Transitional NDRO Josephson Memory Cell

Shuichi Tahara, Y. Wada

A new vortex transitional NDRO memory cell has been proposed for use as a high-speed cache memory. The memory cell consists of two superconducting loops with one Josephson junction and a two-junction interferometer gate. The superconducting loop stores single-flux quantum. The interferometer gate operates as a sense gate. The memory cell employs a vortex transition in the superconducting loop for the writing and reading of data. The sense gate current margin increases to ±38% since the coupling magnetic flux is amplified by the vortex transition for nominally designed cell parameters. The memory cell operates with a ±33% address signal current margin. This paper describes the memory cell design and the dynamic behavior of computer simulations.

Japanese Journal of Applied Physics•Sep 1, 1987•17 citations

An inductively coupled single-flux quantum NDRO memory cell

Kyoko Kojima, T. Noguchi, Koichi Hamanaka

An inductively coupled single-flux quantum nondestructive readout (NDRO) memory cell was fabricated. Control lines of this memory cell are coupled to the main inductance loop. The margin for the damping resistor becomes larger than for a multiflux quantum memory cell. The memory cell containing all return lines occupies only 247 minimum-linewidth squares, on the basis of a 5-µm rule Pb-alloy technique.

IEEE Electron Device Letters•Aug 1, 1983•3 citations
Single flux quantum nondestructive readout (NDRO) Josephson memory cells which store an energy of only ~6/spl times/10/SUP -20/ J have been successfully fabricated and operated for the first time. Margin enhancement due to quantization, and low operating currents render this cell an attractive basis for a <1 ns access-time Josephson cache memory designed with a 2.5 /spl mu/m technology.
A new Single Flux-Quantum (SFQ) Nondestructive Read-Out (NDRO) random-access asymmetric 2-Josephson-junction interferometer memory cell with only one control line has been investigated and designed. The binary information is stored in the cell nonvolatilely without a bias current. For random access, this is the first known interferometer memory cell without a diagonal line. Therefore, this NDRO SFQ memory cell leads intrinsically to smaller cell area and simpler decoder schemes. A cell design of only 52 lithographic squares is given to demonstrate the potential for high-density memory chips. Wide nominal read and write operating margins are obtained. The NDRO interferometer memory cell proposed is promising for use in a high-performance Josephson computer.
Fundamental design criteria for Josephson nondestructive readout random access memory (NDRO RAM) cells are presented, within the context of an LSI array environment. Emphasis is placed upon principles which are relevant to high performance. The criteria are elucidated via a specific design which is simulated and then experimentally evaluated in a technology with a smallest critical dimension of 5 μm. The specific cell differs from previously tested Josephson NDRO cells in several respects; namely, the cell stores only ∼8Φ0, employs interferometer gates and an external damping resistor, allows switching into device resonances, and eliminates the need for a special initialization cycle. The cell-selection scheme, employing triple coincidence, results in larger operating margins and smaller operating currents than have previously been achieved. The large operating margins and all basic cell design criteria were experimentally verified. The experimental interferometer gate characteristics were analyzed in detail and found to be describable by simple models. In addition, it was discovered that single flux quantum transitions in the interferometer gates could be exploited beneficially in order to enhance the insensitivity of operating margins to fabrication tolerances.
A proposal vortex transitional nondestructive read-out Josephson memory cell is successfully fabricated and tested. The memory cell consists of two superconducting loops in which a single flux quantum is stored and a two-junction interferometer gate as a sense gate. The memory cell employs vortex transitions in the superconducting loops for writing and reading data. The vortex transitional memory operation of the cell contributes to improving its sense discrimination and operating margin. The memory cell is activated by two control signals without timing control signals. Memory cell chips have been fabricated using a niobium planarization process. A±21% address signal current margin and a ±33% sense gate current margin have been obtained experimentally. Successful memory operations of a cell driven by two-junction interferometer gates has been demonstrated. The single flux quantum operations of this memory cell makes it an attractive basic element for a high-speed cache memory.
A new vortex transitional NDRO memory cell has been proposed for use as a high-speed cache memory. The memory cell consists of two superconducting loops with one Josephson junction and a two-junction interferometer gate. The superconducting loop stores single-flux quantum. The interferometer gate operates as a sense gate. The memory cell employs a vortex transition in the superconducting loop for the writing and reading of data. The sense gate current margin increases to ±38% since the coupling magnetic flux is amplified by the vortex transition for nominally designed cell parameters. The memory cell operates with a ±33% address signal current margin. This paper describes the memory cell design and the dynamic behavior of computer simulations.