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Journal of Applied Physics

Experimental vortex transitional nondestructive read-out Josephson memory cell

Shuichi Tahara, Ichiro Ishida, Yumi Ajisawa, Yoshifusa Wada

Published Jan 15, 1989• 42 citations
Publisher

Abstract

A proposal vortex transitional nondestructive read-out Josephson memory cell is successfully fabricated and tested. The memory cell consists of two superconducting loops in which a single flux quantum is stored and a two-junction interferometer gate as a sense gate. The memory cell employs vortex transitions in the superconducting loops for writing and reading data. The vortex transitional memory operation of the cell contributes to improving its sense discrimination and operating margin. The memory cell is activated by two control signals without timing control signals. Memory cell chips have been fabricated using a niobium planarization process. A±21% address signal current margin and a ±33% sense gate current margin have been obtained experimentally. Successful memory operations of a cell driven by two-junction interferometer gates has been demonstrated. The single flux quantum operations of this memory cell makes it an attractive basic element for a high-speed cache memory.

DOI
10.1063/1.343077

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A proposal vortex transitional nondestructive read-out Josephson memory cell is successfully fabricated and tested. The memory cell consists of two superconducting loops in which a single flux quantum is stored and a two-junction interferometer gate as a sense gate. The memory cell employs vortex transitions in the superconducting loops for writing and reading data. The vortex transitional memory operation of the cell contributes to improving its sense discrimination and operating margin. The memory cell is activated by two control signals without timing control signals. Memory cell chips have been fabricated using a niobium planarization process. A±21% address signal current margin and a ±33% sense gate current margin have been obtained experimentally. Successful memory operations of a cell driven by two-junction interferometer gates has been demonstrated. The single flux quantum operations of this memory cell makes it an attractive basic element for a high-speed cache memory.
A new vortex transitional NDRO memory cell has been proposed for use as a high-speed cache memory. The memory cell consists of two superconducting loops with one Josephson junction and a two-junction interferometer gate. The superconducting loop stores single-flux quantum. The interferometer gate operates as a sense gate. The memory cell employs a vortex transition in the superconducting loop for the writing and reading of data. The sense gate current margin increases to ±38% since the coupling magnetic flux is amplified by the vortex transition for nominally designed cell parameters. The memory cell operates with a ±33% address signal current margin. This paper describes the memory cell design and the dynamic behavior of computer simulations.
The design and experimental results for a novel type of Josephson memory cell are presented. The cell has a simpler construction than the conventional Henkels-type, using a one-junction SQUID (superconducting quantum interference device) capacitively coupled to a single junction. Binary data are stored as single flux quanta and are destructively read out by sensing a pulse caused by a vortex-mode transition. Computer simulations suggest that the read operation could be performed with a bias margin for the sense junction of +or-28% and that the rise time of the sense current in a 16-bit memory cell would be as fast as 30 ps, despite having to sense a vortex-mode transition. Results are presented for a memory cell fabricated with Nb-AlO/sub x/-Nb junctions.>
The talk is based on an overview which was published recently (1). For this reason, only an abstract is given here, which includes Later results not contained in the aforementioned overview. The presently-known Josephson memory cells store information as persistent currents in superconducting loops, or what is equivalent as a magnetic flux in the area of the ring. This method of storage is nonvolatile and has no power consumption in the storing state. In a superconducting ring system, the magnetic flux is quantized, and cells have been built which operate either with only one flux quantum, or with many of them. For the Latter cells with many flux quanta (ring cells), quite a number of designs exist. They have one or two Josephson junctions in the ring, which allow writing. An external junction which is controlled by the ring current serves for non-destructive reading of the information. The smallest cell realized had an area of 900 ?m2 with a 2 ?m minimum line width. Switching speed was ? 80 ps. Cells which store information as a single-flux quantum (single flux-quantum cells = SFQ cells) in the ring, usually contain two Josephson junctions used for reading and writing. Read-out in most of these cells is destructive, but methods of reading non-destructively have also been proposed. The smallest device made had an area of ? 150 ?m2 with a minimum line width of 2 ?m. The read signal had a rise time ? 100 ps.
Arrays of vortex transitional (VT) memory cells with functional density up to 1 Mbit/cm2have been designed, fabricated, and successfully demonstrated. This progress is due to recent advances in design optimization and in superconductor electronics fabrication achieved at MIT Lincoln Laboratory. As a starting point, we developed a demo array of VT cells for the 100-μA/μm2MIT LL fabrication process SFQ5ee with eight niobium layers. The studied two-junction memory cell with a two-junction nondestructive readout occupied 168 μm2, resulting in an over 0.5 Mbit/cm2functional density. Then, we reduced the cell area down to 99 μm2(corresponding to over 0.9 Mbit/cm2functional density) by utilizing self-shunted Josephson junctions (JJs) with critical current density JC of 600 μA/μm2and eliminating shunt resistors. The fabricated high-JC memory cells were fully operational and possessed wide read/write current margins, quite close to the theoretically predicted values. We discuss approaches to further increasing the integration scale of superconductor memory and logic circuits: 1) miniaturization of superconducting transformers by using soft magnetic materials; and 2) reduction of JJ area by using planar high-JC junctions similar to variable thickness bridges.