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Applied Physics Letters

Single flux-quantum Josephson memory cell using a new threshold characteristic

I. Kurosawa, Akihiko Yagi, Hiroshi Nakagawa, Hisao Hayakawa

Published Dec 1, 1983• 11 citations
Publisher

Abstract

A new single flux-quantum Josephson memory cell in which nondestructive readout (NDRO) operations can be realized with a simple circuit configuration is proposed. The memory cell utilizes a new type of threshold characteristics in an equivalent asymmetric dc superconducting quantum interference device (SQUID) consisting of a three-junction SQUID gate and a single junction. NDRO operation has been successfully demonstrated in an experimental memory circuit.

DOI
10.1063/1.94238

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A new single flux-quantum Josephson memory cell in which nondestructive readout (NDRO) operations can be realized with a simple circuit configuration is proposed. The memory cell utilizes a new type of threshold characteristics in an equivalent asymmetric dc superconducting quantum interference device (SQUID) consisting of a three-junction SQUID gate and a single junction. NDRO operation has been successfully demonstrated in an experimental memory circuit.
An improved single flux-quantum Josephson interferometer memory cell which brought stable nondestructive read-out (NDRO) operation was proposed. The cell was constructed with an end-fed asymmetric two-junction interferometer, in which the bit operating current level could be set far above the critical point for stable NDRO operation. Damping condition for proper memory operation was studied by computer simulation. The NDRO operation was experimentally obtained for the McCumber damping parameter βc of 300–400.
A new Single Flux-Quantum (SFQ) Nondestructive Read-Out (NDRO) random-access asymmetric 2-Josephson-junction interferometer memory cell with only one control line has been investigated and designed. The binary information is stored in the cell nonvolatilely without a bias current. For random access, this is the first known interferometer memory cell without a diagonal line. Therefore, this NDRO SFQ memory cell leads intrinsically to smaller cell area and simpler decoder schemes. A cell design of only 52 lithographic squares is given to demonstrate the potential for high-density memory chips. Wide nominal read and write operating margins are obtained. The NDRO interferometer memory cell proposed is promising for use in a high-performance Josephson computer.
A new vortex transitional NDRO memory cell has been proposed for use as a high-speed cache memory. The memory cell consists of two superconducting loops with one Josephson junction and a two-junction interferometer gate. The superconducting loop stores single-flux quantum. The interferometer gate operates as a sense gate. The memory cell employs a vortex transition in the superconducting loop for the writing and reading of data. The sense gate current margin increases to ±38% since the coupling magnetic flux is amplified by the vortex transition for nominally designed cell parameters. The memory cell operates with a ±33% address signal current margin. This paper describes the memory cell design and the dynamic behavior of computer simulations.
Fundamental design criteria for Josephson nondestructive readout random access memory (NDRO RAM) cells are presented, within the context of an LSI array environment. Emphasis is placed upon principles which are relevant to high performance. The criteria are elucidated via a specific design which is simulated and then experimentally evaluated in a technology with a smallest critical dimension of 5 μm. The specific cell differs from previously tested Josephson NDRO cells in several respects; namely, the cell stores only ∼8Φ0, employs interferometer gates and an external damping resistor, allows switching into device resonances, and eliminates the need for a special initialization cycle. The cell-selection scheme, employing triple coincidence, results in larger operating margins and smaller operating currents than have previously been achieved. The large operating margins and all basic cell design criteria were experimentally verified. The experimental interferometer gate characteristics were analyzed in detail and found to be describable by simple models. In addition, it was discovered that single flux quantum transitions in the interferometer gates could be exploited beneficially in order to enhance the insensitivity of operating margins to fabrication tolerances.
A proposal vortex transitional nondestructive read-out Josephson memory cell is successfully fabricated and tested. The memory cell consists of two superconducting loops in which a single flux quantum is stored and a two-junction interferometer gate as a sense gate. The memory cell employs vortex transitions in the superconducting loops for writing and reading data. The vortex transitional memory operation of the cell contributes to improving its sense discrimination and operating margin. The memory cell is activated by two control signals without timing control signals. Memory cell chips have been fabricated using a niobium planarization process. A±21% address signal current margin and a ±33% sense gate current margin have been obtained experimentally. Successful memory operations of a cell driven by two-junction interferometer gates has been demonstrated. The single flux quantum operations of this memory cell makes it an attractive basic element for a high-speed cache memory.