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IEEE Transactions on Applied Superconductivity

A 6-bit Josephson flash A/D converter with GHz input bandwidth

Paul D. Bradley

Published Mar 1, 1993• 41 citations
Publisher

Abstract

Edge-triggered periodic comparators based on low-inductance superconducting quantum interference devices (SQUIDs) have been combined with a 5-mV step generator used as a clocked power supply to produce an analog-to-digital (A/D) converter with the widest input bandwidth of which the author is aware. The noise and linearity have been measured to be more than adequate for 6 b. Asynchronous beat frequency tests indicate that the current design is capable of about four effective bits resolution at 5-GHz input bandwidth and 3 b at 10 GHz. The aperture jitter at 6-GHz clock rates has been measured to be 100 fs rms indicating that the intrinsic noise is low enough to permit subpicosecond aperture times in faster designs. Further advantages include tolerance of large critical current variations and a sinewave clock as the only high-speed waveform necessary to drive the circuit. The amplitude and spectral purity of the sinewave are not critical as long as it reaches a threshold value, since it is regulated by the step generator.>

DOI
10.1109/77.233533

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IEEE Transactions on Applied Superconductivity•Mar 1, 2004•10 citations
Edge-triggered periodic comparators based on low-inductance superconducting quantum interference devices (SQUIDs) have been combined with a 5-mV step generator used as a clocked power supply to produce an analog-to-digital (A/D) converter with the widest input bandwidth of which the author is aware. The noise and linearity have been measured to be more than adequate for 6 b. Asynchronous beat frequency tests indicate that the current design is capable of about four effective bits resolution at 5-GHz input bandwidth and 3 b at 10 GHz. The aperture jitter at 6-GHz clock rates has been measured to be 100 fs rms indicating that the intrinsic noise is low enough to permit subpicosecond aperture times in faster designs. Further advantages include tolerance of large critical current variations and a sinewave clock as the only high-speed waveform necessary to drive the circuit. The amplitude and spectral purity of the sinewave are not critical as long as it reaches a threshold value, since it is regulated by the step generator.>
This paper presents the progress we have made on our design, fabrication, and testing of a fully parallel superconducting analog-to-digital converter (ADC) with multi-GHz clock frequencies and input bandwidth. To our best knowledge, this converter is the first flash-type analog-to-digital converter ever reported in Josephson technology that fully integrates a quantizer and a thermometer-to-binary encoder to achieve binary outputs. In this design, the quantizer consists of 2(superscript N-1 comparators, each of which is realized using a hysteretic one- junction sampling SQUID driving a two-junction readout SQUID. A new logic family has been designed based on the same comparator building block and has been used to implement the thermometer-to- binary encoder. Taking advantage of the fact that the encoder's input is thermometer-coded, we have designed three-input and four-input quasi-XOR gates with only three NAND gates and therefore reduced significantly the total gate count. Functionalities of all the sub-circuits have been verified experimentally at clock frequencies up to 3 GHz, which is limited by our currently available testing equipment.
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The fabrication and testing of single comparators at low and high speeds (up to 10-GHz input bandwidth) to determine basic functionality, dynamic range, linearity, noise level, and dynamic distortions are described. A 4-b converter was tested at low speed without errors. The results indicate that a 6-b converter may be constructed of these comparators with very good linearity and 8 b should be achievable with slight design modification. The comparator was demonstrated to have an aperture uncertainty>
The authors report on the high-speed operation of a superconducting comparator circuit, based on coupling the quantum flux parametron (QFP) to an RF SQUID, which can be used to build a flash-type analog-to-digital converter (ADC). Simulations of this circuit show that it is expected to achieve operation with input signal bandwidths greater than 4 GHz and with a dynamic range equal to at least 4 b of resolution. A QFP-based comparator fabricated with a process using NbN/Pb-alloy Josephson junctions of 5 mu m by 5 mu m and a current density of 100 A/cm/sup 2/ has been examined to evaluate the properties of the QFP-ADC. Analog-to-digital conversion of the comparator has been observed with a QFP activation frequency up to 18.2 GHz. By employing a sampling method, input signals with frequencies up to 5.4 GHz have also been digitized.>
We compare the SQUID wheel/Quantum Flux Parametron (QFP) comparator to a new Rapid Single Flux Quantum (RSFQ) compatible design. Both have been simulated to demonstrate /spl sim/0.5 ps threshold accuracy which would permit the construction of a flash analog-to-digital converter with six effective bits of resolution at 10 GHz input bandwidth, over three times better than the best performance demonstrated with any technology, At lower input frequencies, both designs have demonstrated that a 10-bit flash ADC is possible. Although simulations of the QFP-based design are more accurate at high signal slew rates due to its symmetry, the RSFQ-based design has a better signal-to-noise ratio and a faster and more flexible clocking scheme which ultimately prove to be more important.
We designed a front-end circuit for an analog-to-digital (A/D) converter based on single flux quantum circuitry and tested its functionality at a frequency of up to 43 GHz. The front-end circuit consisted of a pulse generator, a sigma-delta modulator, a 1-to-8 demultiplexer (DEMUX), and superconducting quantum interference device (SQUID) amplifiers. There were 2518 Josephson junctions in the front-end circuit. To operate the circuit at high speed, we designed robust timing against variations in circuit parameters. By using circuit simulations based on the Monte Carlo method, we estimated spread in time lag between clock and data pulses. From this estimate, the timing was optimized to operate the circuit at 40 GHz. The demonstration of the front-end circuit was carried out using the on-chip testing method. Output data were acquired from the modulator through DEMUX. We confirmed proper sigma-delta modulation by analyzing the dependence of the density "1" in the output data on input current level. The proper operation was confirmed in a range of 37-43 GHz. Furthermore, the amplification by the SQUID amplifier was also confirmed at low speed. These results indicate the complete operation of the front-end circuit for superconductive A/D converter.