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IEEE Transactions on Applied Superconductivity

Design and implementation of an RSFQ switching node for petaflops networks

Shinichi Yorozu, Dmitry Y. Zinoviev, G. Sazaklis

Published Jun 1, 1999• 6 citations
Publisher

Abstract

This work is part of a project to design a petaflops-scale computer using a hybrid technology multi-threaded architecture (HTMT). A high-bandwidth low-latency switching network (CNET) based on RSFQ logic/memory family comprises the core of the superconductor part of the HTMT system, interconnecting 4,096 processors. We present a preliminary low-level design and partial experimental implementation of a multi-credit RSFQ network switching node with the estimated throughput of 7/spl middot/10/sup 10/ 85-bit-parallel packets per second, service latency of 109 ps, and dissipated power of 4.6 mW.

DOI
10.1109/77.783798

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IEEE Transactions on Applied Superconductivity•Jun 1, 1999•4 citations
This work is part of a project to design a petaflops-scale computer using a hybrid technology multi-threaded architecture (HTMT). A high-bandwidth low-latency switching network (CNET) based on RSFQ logic/memory family comprises the core of the superconductor part of the HTMT system, interconnecting 4,096 processors. We present a preliminary low-level design and partial experimental implementation of a multi-credit RSFQ network switching node with the estimated throughput of 7/spl middot/10/sup 10/ 85-bit-parallel packets per second, service latency of 109 ps, and dissipated power of 4.6 mW.
The Hybrid Technology Multi-Threaded (HTMT) approach to petaflops computing includes large numbers of ultra-high performance Nb Rapid Single Flux Quantum (RSFQ) processor and memory chips, making it by far the largest active superconducting electronics project in the United States. In order to achieve petaflops, RSFQ circuits with 10/sup 5/ to 10/sup 6/ junctions per chip will be required to operate at clock speeds of 50 to 100 GHz, far beyond the current state of the art. In this paper, we review the state of the art of Nb circuit fabrication and discuss the requirements for significantly improving circuit density and speed.
Rapid Single Flux Quantum (RSFQ) logic is well-known for its ultra-high switching speed and extremely low power consumption. In this paper, we present two original experiments to demonstrate that it's also a reliable technology and its reliability is sufficient even for such a large-scale system as a proposed petaflops-scale HTMT computer. We have measured the bit error rate (BER) for a circular register of inverters representing a critical path of a 64-bit integer adder, and timing jitter in a 200 Josephson junction (JJ) long transmission line, imitating a branch of a clock distribution tree, both being important and representative building blocks of the HTMT computer. For the adder critical path we have demonstrated the highest clock frequency of 17 GHz, latency of 860 ps and BER of 10/sup -19/ for 3.5 /spl mu/m technology of HYPRES, Inc. The value of timing jitter was 200 fs per JJ for 1.5 /spl mu/m technology of TRW, Inc. These figures are in good agreement with our simulations.
Ultra-low power and ultra-high speed single-flux-quantum electronics is an enabling near-term technology solution for petaflops-scale computers. The proposed Hybrid Technology Multi-threaded (HTMT) petaflops computer architecture includes computational modules operating at 100 GHz and an I/O throughput of 32 Petabits/s. Due to fundamental time-of-flight and power dissipation limitations of semiconductor ICs, superconductor ICs at an integration level of 100 k gates/cm/sup 2/ are proposed for the HTMT computation modules. In this paper, we discuss the manufacturability of superconductor-based computation modules, including the IC foundry process, packaging, and data link out of the cryopackage. We focus on the critical technical challenges that exist in each of these areas and present a technology roadmap to achieve the HTMT requirements.
Internet traffic loads are increasing. Sustaining packet switching throughput of a core node will be difficult. A major reason for this is power consumption and packaging volume. As long as we use only current semiconductor technology, the switching capacity will be limited. Rapid single flux quantum (RSFQ) superconducting technology can overcome such difficulties because of high-speed operation and low-power consumption characteristics. A superconducting wiring also enables high-speed inter-chip communication. We report on progress on packet switch circuit implementation and cryo-cooled packaging for a RSFQ packet switch system. In addition, we discuss a possible packet switch architecture over 100 Tbps that uses RSFQ technology.
We have carried out a paper feasibility study of the implementation of most common packet switching cores (crossbar, Batcher-banyan, time-division shared bus, and token ring) using the superconductor rapid single flux quantum (RSFQ) digital technology. According to our estimates, the best performance-to-complexity ratio may be obtained for the Batcher-banyan network. For example, a 128 by 128 switching core with self-routing (but without address translation, contention resolution, and broadcast features), consisting of about 180,000 Josephson junctions with the internal clock frequency of 60 GHz could handle a workload of 7.5 Tbps. This core could fit on a single 1 cm by 1 cm chip and dissipate as low as 45 mW. The estimated parameters are achievable using a simple 1.5-micrometer niobium- trilayer technology.
We report on the first complete system-level demonstration of a superconducting digital communication system. In today's digital computer and communication systems, managing data flow is a major challenge as the systems have to deal with a huge amount of information. A superconductor device may solve this problem. There have been several attempts to make superconducting switching core circuits, but there have been no complete system-level demonstrations. We have built such a system to demonstrate the efficiency of superconducting devices used in a communication system. Our system is focused on parallel processor communication, and consists of PCs as the processor elements at the three nodes, three interface boxes, and a superconductive chip immersed in a 4.2-K cryostat. The interconnection chip operation is essentially packet switching that was designed with a pipeline ring architecture. The interface box consists of parallel-serial converters, serial-parallel converters, a FIFO output buffer, and a level conversion circuit. The network system operates successfully at approximately 100 MHz, and the clock frequency is restricted by the speed of the interface ICs, not by that of the superconductive chip. We also confirmed the 2-GHz operation of the switching chip, and estimate that the total throughput of the system ran be increased to more than 10 Gbps.