Internet traffic loads are increasing. Sustaining packet switching throughput of a core node will be difficult. A major reason for this is power consumption and packaging volume. As long as we use only current semiconductor technology, the switching capacity will be limited. Rapid single flux quantum (RSFQ) superconducting technology can overcome such difficulties because of high-speed operation and low-power consumption characteristics. A superconducting wiring also enables high-speed inter-chip communication. We report on progress on packet switch circuit implementation and cryo-cooled packaging for a RSFQ packet switch system. In addition, we discuss a possible packet switch architecture over 100 Tbps that uses RSFQ technology.
Internet traffic loads are increasing. Sustaining packet switching throughput of a core node will be difficult. A major reason for this is power consumption and packaging volume. As long as we use only current semiconductor technology, the switching capacity will be limited. Rapid single flux quantum (RSFQ) superconducting technology can overcome such difficulties because of high-speed operation and low-power consumption characteristics. A superconducting wiring also enables high-speed inter-chip communication. We report on progress on packet switch circuit implementation and cryo-cooled packaging for a RSFQ packet switch system. In addition, we discuss a possible packet switch architecture over 100 Tbps that uses RSFQ technology.
With regard to sustaining future capacity of network traffic, the current hardware technology has a big bottleneck in terms of power consumption and insufficient operation speed. To overcome this bottleneck, we have developed a single flux quantum (SFQ) packet-switching circuit. We report recent progress in developing the SFQ packet-switching application. First, we demonstrate a 40 GHz, 160 Gb/s, 4 /spl times/ 4 packet switching circuit, which is currently the fastest clock frequency reported packet switch. Then, we describe a currently possible switching module using SFQ technology. Finally, we consider how SFQ technology can be used to scale the packet-switching capacity up to 100 Tbps.
We have carried out a paper feasibility study of the implementation of most common packet switching cores (crossbar, Batcher-banyan, time-division shared bus, and token ring) using the superconductor rapid single flux quantum (RSFQ) digital technology. According to our estimates, the best performance-to-complexity ratio may be obtained for the Batcher-banyan network. For example, a 128 by 128 switching core with self-routing (but without address translation, contention resolution, and broadcast features), consisting of about 180,000 Josephson junctions with the internal clock frequency of 60 GHz could handle a workload of 7.5 Tbps. This core could fit on a single 1 cm by 1 cm chip and dissipate as low as 45 mW. The estimated parameters are achievable using a simple 1.5-micrometer niobium- trilayer technology.
Large-scale telecommunication systems in the larger nationwide network of the next decade will require routers having a packet switching throughput capacity of over several-tens Tbps. In such future high-end routers, the packet switch, which is the biggest bottleneck of the router, will need higher processing speeds than semiconductor devices. In this paper, we describe an SFQ packet switch architecture that is used in the internal speed-up Banyan network. According to the architecture we have designed and demonstrated a deep-pipelined 2/spl times/2 packet switch logic circuit, which is the key element in a packet switch, by applying two technological advances regarding design methodology and packaging. This circuit is among the largest SFQ random logic circuits yet reported.
This paper describes the results of a preliminary analysis of ultra-fast low-power superconductor digital switches based on Rapid Single-Flux-Quantum (RSFQ) technology. In particular, RSFQ-based crossbar, Batcher-banyan, and shared bus switching cores have been considered, and the possible parameters of these circuits have been estimated. The results show that the proposed RSFQ digital switches with overall throughput of 7.5 Tbps operating at an internal clock frequency of /spl sim/60 GHz and dissipating very little power could effectively compete with their semiconductor and photonic counterparts.
Rapid Single Flux Quantum (RSFQ) Josephson-junction technology is capable of processing digital data at sub-terahertz frequencies while dissipating almost negligible power. At the present time one can routinely simulate, optimize, design, manufacture, and test an elementary RSFQ logic/memory cell consisting of dozens of Josephson junctions. Furthermore, a number of relatively complex (few hundred to few thousand Josephson junctions) digital circuits were designed and successfully tested. Moreover we know how to implement several RSFQ systems (including analog-to-digital and digital-to-analog converters, digital SQUIDs for supersensitive magnetometry, and digital autocorrelator for radioastronomy) which would far outperform their currently available and even prospective semiconductor counterparts. In order to implement more complex RSFQ systems, including high-performance digital signal processors and general purpose computers there are a number of technical problems to solve. The issues include making full use of on-chip sub-terahertz processing in conditions when inter-chip data/clock exchange speed is bound by bandwidth of the order of a few Gbps/pin. I present the current know-how of the field, and formulate the questions that need to be solved before the RSFQ technology becomes a major workhorse of high-performance computation.
Rapid Single-Flux-Quantum (RSFQ) logic is a superconductor IC technology that, with only a modest number of researchers worldwide, has produced some of the world's highest performance digital and mixed-signal circuits. This achievement is due, in part, to a constellation of characteristics that manifest themselves at the circuit level – namely, high-speed digital logic at low-power, ideal interconnects, quantum accuracy, scalability, and simplicity of fabrication. A necessary key to translating these advantages to the system-level involves understanding the I/O, synchronization, and packaging issues associated with a cryogenic technology. The objective of this paper is to review the status of current RSFQ circuit-level infrastructure components and their potential impact on system-level applications.