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IEEE-NPSS Real-Time Conference

A data transmission and time measurement system for bit commitment experiment

Hongfei Zhang, Jian Wang, Ke Cui, Sheng-zhao Lin, Dong-xu Yang, Jian Wang

Published May 1, 2014• 1 citation
Publisher

Abstract

A data transmission and time measurement system for bit commitment experiment is introduced in this paper. The design is for requirement of fast data transmission and time measurement of bit commitment experiment including high bandwidth data transmission, storage, real time processing with FPGA, USB 2.0, FPGA-based TDC and TDC-GPX for time measurement. The system is applied in the bit commitment experiments successfully.

DOI
10.1109/rtc.2014.7097554

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A data transmission and time measurement system for bit commitment experiment is introduced in this paper. The design is for requirement of fast data transmission and time measurement of bit commitment experiment including high bandwidth data transmission, storage, real time processing with FPGA, USB 2.0, FPGA-based TDC and TDC-GPX for time measurement. The system is applied in the bit commitment experiments successfully.
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Quantum key distribution (QKD) is the most matured application of quantum communication. The time synchronization and system timing jitter are essential to a practical QKD experiment, which can directly influence the quantum bit error rate (QBER) and the final key rate. High precision time-to-digital converters (TDCs) can effectively reduce the system timing jitter, resulting in lower QBER and higher key rate. Here, we introduce a TDC based on a field programmable gate array (FPGA). Its high resolution (LSB) of 50 ps with precision (RMS) less than 50 ps, low dead time and large dynamic range can well meet the requirement of the QKD experiment. A free space QKD system setup using the FPGA-based TDC has been assembled. The timing precision of the synchronous light and the system timing jitter were determined. The results demonstrate that the FPGA-based TDC could be successfully applied in the QKD experiment.
Quantum key distribution (QKD) is the most matured application of quantum communication. The time synchronization and system timing jitter are essential to a practical QKD experiment, which can directly influence the quantum bit error rate (QBER) and the final key rate. High precision time-to-digital convertor (TDC) can effectively reduce the system timing jitter, resulting in lower QBER and higher key rate. Here, we introduce a TDC based on a field-programmable gate array (FPGA). Its high resolution of 50 ps, low dead time and large dynamic range can well meet the requirement of the QKD experiment. A free space QKD system setup using the FPGA-based TDC has been built up. The timing precision of the synchronous light and the system timing jitter were tested. The results demonstrate that the FPGA-based TDC could be successfully applied in the QKD experiment.
At the long-distance quantum key distribution(QKD) experiments,high-speed quantum transmission is needed.In this paper,quantum transmission rate at 500 Mbit/s is fulfilled based on SER/DES module inside FPGA,and a time synchronization design between transmitter and receiver using a low frequency sync-pulse(2 MHz) is proposed.For the experiment′s requirements,signal discriminator,pseudo-random number generator,time synchronization and data coding are developed.This design has been applied successfully to build decoy-state based long-distance QKD experiment.
A universal serial bus(USB) based design of high speed data channel for quantum key distribution(QKD) system is introduced in this paper.Through analyzing the data transfer requirement in classic channel of QKD,we propose this USB-based scheme.By means of testing the actual speed of USB data channel,the proper USB-relevant parameters are obtained.The experiment results show that the proposed USB design is suitable for QKD system with 20 MHz photon transmitting frequency,and there is still enough bandwidth of the USB module,so it is convenient to use this module in other QKD systems which require higher-speed transmission.
High-resolution time measurement is a fundamental building block on a wide variety of applications such as time-of-flight based systems, single-photon microscopy and quantum communications. FPGA-based TDCs are the preferred choice for cost-effective implementations requiring both high performance and flexibility. In this work, a Tapped-Delay Line (TDL) and Wave Union Tapped-Delay Line (WU TDL) TDC architectures are implemented and characterized on a Zynq Ultrascale+ FPGA-board. The characterization will mainly focus on determining the resolution and linearity of both TDCs. A bin merging algorithm is also tested to see the increment of linearity at expense of resolution. The TDL and WU TDL implementations were tested measuring the time difference of two signals obtaining 11.6 ps and 11.4 ps RMS resolution respectively. The achieved performance allow the proposed implementations to be integrated in high-resolution time measuring systems.