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FPGA-based TDC for QKD

Compte Prades, Joel

Published Sep 6, 2023• 0 citations
OpenAlex

Abstract

High-resolution time measurement is a fundamental building block on a wide variety of applications such as time-of-flight based systems, single-photon microscopy and quantum communications. FPGA-based TDCs are the preferred choice for cost-effective implementations requiring both high performance and flexibility. In this work, a Tapped-Delay Line (TDL) and Wave Union Tapped-Delay Line (WU TDL) TDC architectures are implemented and characterized on a Zynq Ultrascale+ FPGA-board. The characterization will mainly focus on determining the resolution and linearity of both TDCs. A bin merging algorithm is also tested to see the increment of linearity at expense of resolution. The TDL and WU TDL implementations were tested measuring the time difference of two signals obtaining 11.6 ps and 11.4 ps RMS resolution respectively. The achieved performance allow the proposed implementations to be integrated in high-resolution time measuring systems.

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High-resolution time measurement is a fundamental building block on a wide variety of applications such as time-of-flight based systems, single-photon microscopy and quantum communications. FPGA-based TDCs are the preferred choice for cost-effective implementations requiring both high performance and flexibility. In this work, a Tapped-Delay Line (TDL) and Wave Union Tapped-Delay Line (WU TDL) TDC architectures are implemented and characterized on a Zynq Ultrascale+ FPGA-board. The characterization will mainly focus on determining the resolution and linearity of both TDCs. A bin merging algorithm is also tested to see the increment of linearity at expense of resolution. The TDL and WU TDL implementations were tested measuring the time difference of two signals obtaining 11.6 ps and 11.4 ps RMS resolution respectively. The achieved performance allow the proposed implementations to be integrated in high-resolution time measuring systems.
We present a Time-to-Digital Converter (TDC) implemented on a 16 nm Xilinx UltraScale Plus FPGA that achieves a resolution of 1.15 ps, RMS precision of 3.38 ps, a differential nonlinearity (DNL) of [-0.43, 0.24] LSB, and an integral nonlinearity (INL) of [-2.67, 0.15] LSB. This work introduces two novel hardware-independent post-processing techniques - Partial Order Reconstruction (POR) and Iterative Time-bin Interleaving (ITI) - that significantly enhance the performance of FPGA-based TDCs. POR addresses the missing code problem by inferring the partial order of each time bin through code density test data and directed acyclic graph (DAG) analysis, enabling near-complete recovery of usable bins. ITI further improves fine time resolution by merging multiple calibrated tapped delay lines (TDLs) into a single unified delay chain, achieving scalable resolution without resorting to averaging. Compared to state-of-the-art FPGA-based TDC architectures, the proposed methods deliver competitive or superior performance with reduced hardware overhead. These techniques are broadly applicable to high-resolution time measurement and precise delay calibration in programmable logic platforms.
Intrinsic nonlinearity in FPGA-based time-to-digital converters (TDCs) is often treated as a calibration issue and evaluated mainly through post-correction metrics. In quantum key distribution (QKD), however, raw delay-line nonuniformity can affect coincidence timing and thereby influence accidental-coincidence rate and Quantum Bit Error Rate (QBER). This paper analyzes how measured FPGA-TDC nonlinearity propagates to QKD timing metrics using a conservative system-level model that combines random timing uncertainty and deterministic nonlinearity. We also propose fabric-level mitigation strategies based on LUT-assisted delay shaping and placement constraints to reduce severe bin-width irregularities without statistical calibrations. The method is evaluated by reproducing two open-source TDCs implemented on a low-cost Zynq-7000 FPGA. We observe reductions of 14\%-21\% in integral nonlinearity (INL) compared with the non-optimized design, leading to a reduced QBER contribution and an improvement by 3.7\%-14.2\% in the estimated secret fraction. These results suggest that raw FPGA-TDC nonlinearity deserves explicit consideration in timing-sensitive QKD implementations.
Quantum key distribution (QKD) is the most matured application of quantum communication. The time synchronization and system timing jitter are essential to a practical QKD experiment, which can directly influence the quantum bit error rate (QBER) and the final key rate. High precision time-to-digital converters (TDCs) can effectively reduce the system timing jitter, resulting in lower QBER and higher key rate. Here, we introduce a TDC based on a field programmable gate array (FPGA). Its high resolution (LSB) of 50 ps with precision (RMS) less than 50 ps, low dead time and large dynamic range can well meet the requirement of the QKD experiment. A free space QKD system setup using the FPGA-based TDC has been assembled. The timing precision of the synchronous light and the system timing jitter were determined. The results demonstrate that the FPGA-based TDC could be successfully applied in the QKD experiment.
Quantum key distribution (QKD) is the most matured application of quantum communication. The time synchronization and system timing jitter are essential to a practical QKD experiment, which can directly influence the quantum bit error rate (QBER) and the final key rate. High precision time-to-digital convertor (TDC) can effectively reduce the system timing jitter, resulting in lower QBER and higher key rate. Here, we introduce a TDC based on a field-programmable gate array (FPGA). Its high resolution of 50 ps, low dead time and large dynamic range can well meet the requirement of the QKD experiment. A free space QKD system setup using the FPGA-based TDC has been built up. The timing precision of the synchronous light and the system timing jitter were tested. The results demonstrate that the FPGA-based TDC could be successfully applied in the QKD experiment.
The paper presents a system for measuring photon statistics and photon timing in the few-photon regime down to the single-photon level. The measurement system is based on superconducting nanowire single photon detectors and a time-to-digital converter implemented into a programmable device. The combination of these devices gives high performance to the system in terms of resolution and adaptability to the actual experimental conditions. As a case of application, we present the measurement of photon statistics for coherent light states. In this measurement, we make use of 8th order single photon correlations to reconstruct with high fidelity the statistics of a coherent state with average photon number up to 4. The processing is performed by means of a tapped-delay-line time-to-digital converter architecture that also hosts an asynchronous-correlated-digital-counter implemented in a field programmable gate array device and specifically designed for performance optimization in multi-channel usage.
Time-to-Digital Converters (TDCs) are a crucial tool in a wide array of fields, in particular for quantum communication, where time taggers performance can severely affect the quality of the entire application. Nowadays, FPGA-based TDCs present a viable alternative to ASIC ones, once the non-linear behavior due to the intrinsic nature of the device is properly mitigated. To compensate for said nonlinearities, a calibration procedure is required, which should be maintained throughout its runtime. Here we present the design and the demonstration of a TDC that is FPGA-based showing a residual FWHM jitter of 27 ps, that is scalable for multichannel operation. The target application in Quantum Key Distribution (QKD) is discussed with a calibration method based on the exploitation of single-photon detection that does not require stopping the data acquisition or using any estimation methods, thus increasing accuracy and removing data loss. The calibration was tested in a relevant environment, investigating the behavior of the device between 5 °C and 80 °C. Moreover, our design is capable of continuously streaming up to 12 Mevents/s for up to ~1 week without the TDC overflowing making it ready for a real-life scenario deployment.