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arXiv:2511.05583

Delay Time Characterization on FPGA: A Low Nonlinearity, Picosecond Resolution Time-to-Digital Converter on 16-nm FPGA using Bin Sequence Calibration

Sunwoo Park, Byungkwon Park, Eunsung Kim, Jiwon Yune, Seungho Han, Seunggo Nam

cs.ARphysics.ins-detquant-phSubmitted Nov 5, 2025• Announced Nov 6, 2025
arXivHTMLPDF

Abstract

We present a Time-to-Digital Converter (TDC) implemented on a 16 nm Xilinx UltraScale Plus FPGA that achieves a resolution of 1.15 ps, RMS precision of 3.38 ps, a differential nonlinearity (DNL) of [-0.43, 0.24] LSB, and an integral nonlinearity (INL) of [-2.67, 0.15] LSB. This work introduces two novel hardware-independent post-processing techniques - Partial Order Reconstruction (POR) and Iterative Time-bin Interleaving (ITI) - that significantly enhance the performance of FPGA-based TDCs. POR addresses the missing code problem by inferring the partial order of each time bin through code density test data and directed acyclic graph (DAG) analysis, enabling near-complete recovery of usable bins. ITI further improves fine time resolution by merging multiple calibrated tapped delay lines (TDLs) into a single unified delay chain, achieving scalable resolution without resorting to averaging. Compared to state-of-the-art FPGA-based TDC architectures, the proposed methods deliver competitive or superior performance with reduced hardware overhead. These techniques are broadly applicable to high-resolution time measurement and precise delay calibration in programmable logic platforms.

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FPGA-based TDC for QKD

Compte Prades, Joel

High-resolution time measurement is a fundamental building block on a wide variety of applications such as time-of-flight based systems, single-photon microscopy and quantum communications. FPGA-based TDCs are the preferred choice for cost-effective implementations requiring both high performance and flexibility. In this work, a Tapped-Delay Line (TDL) and Wave Union Tapped-Delay Line (WU TDL) TDC architectures are implemented and characterized on a Zynq Ultrascale+ FPGA-board. The characterization will mainly focus on determining the resolution and linearity of both TDCs. A bin merging algorithm is also tested to see the increment of linearity at expense of resolution. The TDL and WU TDL implementations were tested measuring the time difference of two signals obtaining 11.6 ps and 11.4 ps RMS resolution respectively. The achieved performance allow the proposed implementations to be integrated in high-resolution time measuring systems.

•Sep 6, 2023•0 citations

A Security-Aware Nonlinearity Study of FPGA-Based Time-to-Digital Converters for Quantum Key Distribution Systems

Kun Qin, Carsten Trinitis

Intrinsic nonlinearity in FPGA-based time-to-digital converters (TDCs) is often treated as a calibration issue and evaluated mainly through post-correction metrics. In quantum key distribution (QKD), however, raw delay-line nonuniformity can affect coincidence timing and thereby influence accidental-coincidence rate and Quantum Bit Error Rate (QBER). This paper analyzes how measured FPGA-TDC nonlinearity propagates to QKD timing metrics using a conservative system-level model that combines random timing uncertainty and deterministic nonlinearity. We also propose fabric-level mitigation strategies based on LUT-assisted delay shaping and placement constraints to reduce severe bin-width irregularities without statistical calibrations. The method is evaluated by reproducing two open-source TDCs implemented on a low-cost Zynq-7000 FPGA. We observe reductions of 14\%-21\% in integral nonlinearity (INL) compared with the non-optimized design, leading to a reduced QBER contribution and an improvement by 3.7\%-14.2\% in the estimated secret fraction. These results suggest that raw FPGA-TDC nonlinearity deserves explicit consideration in timing-sensitive QKD implementations.

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An FPGA-Based TDC for Free Space Quantum Key Distribution

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Quantum key distribution (QKD) is the most matured application of quantum communication. The time synchronization and system timing jitter are essential to a practical QKD experiment, which can directly influence the quantum bit error rate (QBER) and the final key rate. High precision time-to-digital converters (TDCs) can effectively reduce the system timing jitter, resulting in lower QBER and higher key rate. Here, we introduce a TDC based on a field programmable gate array (FPGA). Its high resolution (LSB) of 50 ps with precision (RMS) less than 50 ps, low dead time and large dynamic range can well meet the requirement of the QKD experiment. A free space QKD system setup using the FPGA-based TDC has been assembled. The timing precision of the synchronous light and the system timing jitter were determined. The results demonstrate that the FPGA-based TDC could be successfully applied in the QKD experiment.

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Demonstration of Picosecond Time Resolution in Double-Oscillator Time-to-Digital Converter Using Single-Flux-Quantum Circuits

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We have been developing a time-to-digital converter (TDC) using single-flux-quantum (SFQ) circuits in order to realize an imaging system based on a superconducting strip single-photon detector (SSPD). In this system, the absorption position of a single photon in a meander-shaped SSPD is determined by measuring the delay time of the detected signal propagating through an SSPD delay line. Increasing the time resolution of the TDC is the primary concern for improving the spatial resolution of the system. Here we focused on the double-oscillator SFQ TDC, where the difference of oscillation periods between two SFQ ring oscillators determines the time resolution. In the previous study, a time resolution of about 4 ps was demonstrated by using the Nb standard Josephson integrated circuit (IC) process with a critical current density of 2.5 kA/cm2. In this study, we improved the time resolution by adopting the Nb advanced Josephson IC process with a critical current density of 10 kA/cm2and by optimizing the circuit parameters of the coincidence detector. The histogram and the linearity of the delay measurements show that the time resolution is improved to up to 2 ps.

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Time-to-Digital Converters (TDCs) are a crucial tool in a wide array of fields, in particular for quantum communication, where time taggers performance can severely affect the quality of the entire application. Nowadays, FPGA-based TDCs present a viable alternative to ASIC ones, once the non-linear behavior due to the intrinsic nature of the device is properly mitigated. To compensate for said nonlinearities, a calibration procedure is required, which should be maintained throughout its runtime. Here we present the design and the demonstration of a TDC that is FPGA-based showing a residual FWHM jitter of 27 ps, that is scalable for multichannel operation. The target application in Quantum Key Distribution (QKD) is discussed with a calibration method based on the exploitation of single-photon detection that does not require stopping the data acquisition or using any estimation methods, thus increasing accuracy and removing data loss. The calibration was tested in a relevant environment, investigating the behavior of the device between 5 °C and 80 °C. Moreover, our design is capable of continuously streaming up to 12 Mevents/s for up to ~1 week without the TDC overflowing making it ready for a real-life scenario deployment.

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A Precise High Count-Rate FPGA Based Multi-Channel Coincidence Counting System for Quantum Photonics Applications

E. Arabul, Stefano Paesani, Scott Tancock +2 more

Coincidence counters play the role of gating events from the background noise in almost every quantum photonics setup. Precise multi-channel and high count-rate coincidence counting tools have become desirable due to an increase in the complexity of quantum photonics experiments. However, timing analyzers are struggling to meet these needs. We are proposing a Field Programmable Gate Array (FPGA) based coincidence counting system which provides 8 operational channels with 8.9 ps root mean square (RMS) resolution (with a bin width of 7.7 ps) and a count-rate of 320 million counts per second (MCPS) (with 40 MCPS per channel). We have successfully tested our design in different quantum photonics scenarios such as the detection of two-photon interference and pseudo-photon-number resolving detection of a coherent state of light where it has shown its capability of working beyond the saturation of detectors. Also, we have introduced a Dual Data Rate Registration TDC, which improved the linearity of the time tagging operation by using both clock edges without increasing the dead-time or using the space excessively. 1.2 LSB in max DNL error, 1.8 LSB in max INL error, 10 ps in FWHM and 3.2 ps in RMS resolution improvements were achieved.

IEEE photonics journal•Jan 22, 2020•17 citations
We present a Time-to-Digital Converter (TDC) implemented on a 16 nm Xilinx UltraScale Plus FPGA that achieves a resolution of 1.15 ps, RMS precision of 3.38 ps, a differential nonlinearity (DNL) of [-0.43, 0.24] LSB, and an integral nonlinearity (INL) of [-2.67, 0.15] LSB. This work introduces two novel hardware-independent post-processing techniques - Partial Order Reconstruction (POR) and Iterative Time-bin Interleaving (ITI) - that significantly enhance the performance of FPGA-based TDCs. POR addresses the missing code problem by inferring the partial order of each time bin through code density test data and directed acyclic graph (DAG) analysis, enabling near-complete recovery of usable bins. ITI further improves fine time resolution by merging multiple calibrated tapped delay lines (TDLs) into a single unified delay chain, achieving scalable resolution without resorting to averaging. Compared to state-of-the-art FPGA-based TDC architectures, the proposed methods deliver competitive or superior performance with reduced hardware overhead. These techniques are broadly applicable to high-resolution time measurement and precise delay calibration in programmable logic platforms.
High-resolution time measurement is a fundamental building block on a wide variety of applications such as time-of-flight based systems, single-photon microscopy and quantum communications. FPGA-based TDCs are the preferred choice for cost-effective implementations requiring both high performance and flexibility. In this work, a Tapped-Delay Line (TDL) and Wave Union Tapped-Delay Line (WU TDL) TDC architectures are implemented and characterized on a Zynq Ultrascale+ FPGA-board. The characterization will mainly focus on determining the resolution and linearity of both TDCs. A bin merging algorithm is also tested to see the increment of linearity at expense of resolution. The TDL and WU TDL implementations were tested measuring the time difference of two signals obtaining 11.6 ps and 11.4 ps RMS resolution respectively. The achieved performance allow the proposed implementations to be integrated in high-resolution time measuring systems.
Intrinsic nonlinearity in FPGA-based time-to-digital converters (TDCs) is often treated as a calibration issue and evaluated mainly through post-correction metrics. In quantum key distribution (QKD), however, raw delay-line nonuniformity can affect coincidence timing and thereby influence accidental-coincidence rate and Quantum Bit Error Rate (QBER). This paper analyzes how measured FPGA-TDC nonlinearity propagates to QKD timing metrics using a conservative system-level model that combines random timing uncertainty and deterministic nonlinearity. We also propose fabric-level mitigation strategies based on LUT-assisted delay shaping and placement constraints to reduce severe bin-width irregularities without statistical calibrations. The method is evaluated by reproducing two open-source TDCs implemented on a low-cost Zynq-7000 FPGA. We observe reductions of 14\%-21\% in integral nonlinearity (INL) compared with the non-optimized design, leading to a reduced QBER contribution and an improvement by 3.7\%-14.2\% in the estimated secret fraction. These results suggest that raw FPGA-TDC nonlinearity deserves explicit consideration in timing-sensitive QKD implementations.
Quantum key distribution (QKD) is the most matured application of quantum communication. The time synchronization and system timing jitter are essential to a practical QKD experiment, which can directly influence the quantum bit error rate (QBER) and the final key rate. High precision time-to-digital converters (TDCs) can effectively reduce the system timing jitter, resulting in lower QBER and higher key rate. Here, we introduce a TDC based on a field programmable gate array (FPGA). Its high resolution (LSB) of 50 ps with precision (RMS) less than 50 ps, low dead time and large dynamic range can well meet the requirement of the QKD experiment. A free space QKD system setup using the FPGA-based TDC has been assembled. The timing precision of the synchronous light and the system timing jitter were determined. The results demonstrate that the FPGA-based TDC could be successfully applied in the QKD experiment.
We have been developing a time-to-digital converter (TDC) using single-flux-quantum (SFQ) circuits in order to realize an imaging system based on a superconducting strip single-photon detector (SSPD). In this system, the absorption position of a single photon in a meander-shaped SSPD is determined by measuring the delay time of the detected signal propagating through an SSPD delay line. Increasing the time resolution of the TDC is the primary concern for improving the spatial resolution of the system. Here we focused on the double-oscillator SFQ TDC, where the difference of oscillation periods between two SFQ ring oscillators determines the time resolution. In the previous study, a time resolution of about 4 ps was demonstrated by using the Nb standard Josephson integrated circuit (IC) process with a critical current density of 2.5 kA/cm2. In this study, we improved the time resolution by adopting the Nb advanced Josephson IC process with a critical current density of 10 kA/cm2and by optimizing the circuit parameters of the coincidence detector. The histogram and the linearity of the delay measurements show that the time resolution is improved to up to 2 ps.
Time-to-Digital Converters (TDCs) are a crucial tool in a wide array of fields, in particular for quantum communication, where time taggers performance can severely affect the quality of the entire application. Nowadays, FPGA-based TDCs present a viable alternative to ASIC ones, once the non-linear behavior due to the intrinsic nature of the device is properly mitigated. To compensate for said nonlinearities, a calibration procedure is required, which should be maintained throughout its runtime. Here we present the design and the demonstration of a TDC that is FPGA-based showing a residual FWHM jitter of 27 ps, that is scalable for multichannel operation. The target application in Quantum Key Distribution (QKD) is discussed with a calibration method based on the exploitation of single-photon detection that does not require stopping the data acquisition or using any estimation methods, thus increasing accuracy and removing data loss. The calibration was tested in a relevant environment, investigating the behavior of the device between 5 °C and 80 °C. Moreover, our design is capable of continuously streaming up to 12 Mevents/s for up to ~1 week without the TDC overflowing making it ready for a real-life scenario deployment.
Coincidence counters play the role of gating events from the background noise in almost every quantum photonics setup. Precise multi-channel and high count-rate coincidence counting tools have become desirable due to an increase in the complexity of quantum photonics experiments. However, timing analyzers are struggling to meet these needs. We are proposing a Field Programmable Gate Array (FPGA) based coincidence counting system which provides 8 operational channels with 8.9 ps root mean square (RMS) resolution (with a bin width of 7.7 ps) and a count-rate of 320 million counts per second (MCPS) (with 40 MCPS per channel). We have successfully tested our design in different quantum photonics scenarios such as the detection of two-photon interference and pseudo-photon-number resolving detection of a coherent state of light where it has shown its capability of working beyond the saturation of detectors. Also, we have introduced a Dual Data Rate Registration TDC, which improved the linearity of the time tagging operation by using both clock edges without increasing the dead-time or using the space excessively. 1.2 LSB in max DNL error, 1.8 LSB in max INL error, 10 ps in FWHM and 3.2 ps in RMS resolution improvements were achieved.