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IEEE Transactions on Magnetics

Simplified fabrication of magnetically coupled Josephson circuits

L. N. Smith, D. W. Jillie, Harry Kroger

Published Mar 1, 1985• 4 citations
Publisher

Abstract

We describe a technique for fabricating magnetically coupled Josephson logic and memory circuits and SQUIDs which uses only two superconducting layers. These two layers perform multiple functions as the base and counterelectrodes of the tunnel junctions, the SQUID inductance and control lines, and the signal lines and groundplane between gates. This technique is illustrated by the specific example of a two junction, resistively damped SQUID designed to be fabricated using an all-refractory process which employs a total of five masking levels.

DOI
10.1109/tmag.1985.1063740

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We describe a technique for fabricating magnetically coupled Josephson logic and memory circuits and SQUIDs which uses only two superconducting layers. These two layers perform multiple functions as the base and counterelectrodes of the tunnel junctions, the SQUID inductance and control lines, and the signal lines and groundplane between gates. This technique is illustrated by the specific example of a two junction, resistively damped SQUID designed to be fabricated using an all-refractory process which employs a total of five masking levels.
Flux quantum logic and memory circuits using superconducting Josephson tunnel junctions have high-speed switching times (approximately 1 ps), low power dissipation (< 1 (mu) W per circuit) and low levels of thermally induced electrical noise. Current designs of such circuits employ single trilayer junctions, which impose circuit size and logic threshold limitations. A new design component, the multilayered tunnel junction, consists of a vertically stacked array (a 1D superlattice) of Josephson tunnel junctions. The introduction of multilayered junctions into superconducting electronic circuitry offers a reduction in the current device size, fault tolerances, and new device applications. We present numerical simulations of simple circuits employing multilayered Josephson junctions as design components. Comparison with conventional single flux quantum circuitry is discussed. We also present preliminary measurements of multilayered Josephson junctions fabricated for use in flux quantum devices.
A novel process suitable for fabricating superconducting circuitry based on the all refractory material NbN is described. In this process, an in-situ trilayer film composed of NbN/MgO/NbN is used to fabricate Josephson tunnel junctions. Reactive ion etching processes are used to delineate devices and pattern insulators and metallizations. Fabricated junctions have yielded good tunneling characteristics with reasonable current density uniformity and reproducibility. Devices with gap voltages close to 5mV have been achieved for high quality junctions. In addition to the trilayer, there are two wiring layers, two resistor depositions, and two insulation layers, constituting a full NbN based fabrication technology. Using this process, we fabricated and successfully tested thin film DC SQUID and time domain reflectometer (TDR) circuits. Preliminary measurements suggest that the critical temperature of these circuits is well within the operating temperature of commercial two-stage closed cycle refrigerators.
All refractory Josephson loop logic circuits for a 1Kbit SFQ memory have been developed. The circuit fabircation technology, using NbN/Nb double layered junction formation and reactive ion etching(RIE)with a 2.5μm minimum feature size and 1.5μm overlay registration, has been utilized. A highly selective and anisotropic RIE process has been performed, in which a CCl2F2+ Ne gas mixture has been used as etching gases. The experimental circuit consists of address decoders and line drivers, which are based on the principle of current steering in superconducting loops. The decoder and driver were successfully operated with the gate current margin of ±18% and ±14%, respectively. The decoder internal delay time was measured to be about 1.5 ns. It is revealed that these circuits have a satisfactory preformance to be used in the 1Kbit SFQ memory.
We successfully fabricated magnetic Josephson junctions integrated on a Nb four-layer superconducting structure for demonstrating half flux quantum (HFQ) circuits. In the developed process, we adopted a 0-0-π SQUID instead of the 0-π SQUID as the basic element of the HFQ circuits. In this work, we characterized the Nb/PdNi/Nb magnetic Josephson junctions on the Nb four-layer structures fabricated by two different processes. We measured the I-V characteristics of junctions in liquid helium at 4.2 K. The results showed that the fabricated junctions had properties comparable to conventional ones on Si wafers.
The authors have developed two distinct processes for the fabrication of mesoscopic Josephson junction qubits that are compatible with conventional CMOS processing. These devices, based on superconducting Al/Al2O3/Al tunnel junctions, are fabricated by electron beam lithography using single-layer and multi-layer resists. The new single-layer resist process is found to have significant advantages over conventional fabrication methods using suspended tri-layer shadow masks. It is simpler and more accurate to implement, and avoids the significant areas of redundant metallisation that are an unavoidable by-product of the tri-layer shadow mask method.
We have developed a novel process for fabricating all refractory Josephson tunnel junctions whose base and counter electrodes are composed of (Nb-NbN) double-layered films. In this process, tunnel junctions have been isolated using a reactive ion etching from a junction sandwich which had been formed on an entire silicon wafer, and also the reactive ion etching has been used for patterning electrodes and insulation layers in devices. Fabricated junctions have yielded good tunneling characteristics with excellent uniformity and reproducibility. The maximum critical current density was widely changed from 300 A/cm2to 8 kA/cm2. All refractory single flux quantum(SFQ) memory cells in a 32×32 arrangement have been integrated with a 2.5 μm minimum linewidth on a chip using this process, and an SFQ cell in the memory array has been successfully operated. The maximum deviation of critical currents in the memory array was measured to be ±6.5%.