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Proceedings of SPIE, the International Society for Optical Engineering/Proceedings of SPIE

Multilayered Josephson junction logic and memory devices

Susanne Lomatch, E. D. Rippert, John B. Ketterson

Published Jun 29, 1994• 2 citations
Publisher

Abstract

Flux quantum logic and memory circuits using superconducting Josephson tunnel junctions have high-speed switching times (approximately 1 ps), low power dissipation (< 1 (mu) W per circuit) and low levels of thermally induced electrical noise. Current designs of such circuits employ single trilayer junctions, which impose circuit size and logic threshold limitations. A new design component, the multilayered tunnel junction, consists of a vertically stacked array (a 1D superlattice) of Josephson tunnel junctions. The introduction of multilayered junctions into superconducting electronic circuitry offers a reduction in the current device size, fault tolerances, and new device applications. We present numerical simulations of simple circuits employing multilayered Josephson junctions as design components. Comparison with conventional single flux quantum circuitry is discussed. We also present preliminary measurements of multilayered Josephson junctions fabricated for use in flux quantum devices.

DOI
10.1117/12.179165

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Flux quantum logic and memory circuits using superconducting Josephson tunnel junctions have high-speed switching times (approximately 1 ps), low power dissipation (< 1 (mu) W per circuit) and low levels of thermally induced electrical noise. Current designs of such circuits employ single trilayer junctions, which impose circuit size and logic threshold limitations. A new design component, the multilayered tunnel junction, consists of a vertically stacked array (a 1D superlattice) of Josephson tunnel junctions. The introduction of multilayered junctions into superconducting electronic circuitry offers a reduction in the current device size, fault tolerances, and new device applications. We present numerical simulations of simple circuits employing multilayered Josephson junctions as design components. Comparison with conventional single flux quantum circuitry is discussed. We also present preliminary measurements of multilayered Josephson junctions fabricated for use in flux quantum devices.
We describe the properties of flux quantum circuitry employing the relatively young technology of multilayer Josephson junctions with n superconductor-insulator (SI) layers. Multilayer junctions can be employed as both passive and active devices to increase circuit integration density, allow for new logic/voltage thresholds and higher impedances, and improve thermal noise stability. We present the results from numerical simulations of a conventional RSFQ circuit and two novel circuits with multilayer junction designs. Neural circuitry is a focus of our novel multilayer designs. We also discuss layout and fabrication issues, considering the recent progress in the fabrication of Nb multilayer junctions with AlN tunnel barriers, which exhibit intrinsic overdamping at the level of each SI layer. Included in this discussion is a long term assessment of a multilayer approach in view of deep sub-micron and high T/sub c/ technologies.>
We present a new type of Josephson transmission line (JTL) in which discrete multilayer Josephson junctions are employed instead of the standard single tri-layer junction technology. It is shown via numerical simulation that such a structure supports the propagation of multiple flux quantum solitons, which are represented in this system by a 2πn kink in the phase difference across a multilayer junction of n superconductor-insulator-superconductor layers. As a practical aspect, parallel and series connected multilayer junctions in a JTL can significantly reduce the need for microstrip line inductance, thereby providing the optimal conditions for large scale integration of JTL-based logic and memory circuitry. In this article we investigate in detail through numerical simulation the properties of JTL designs with multilayer junctions, incorporating expected variations in junction characteristics. A brief description of the current fabrication of multilayer junctions for flux quantum circuitry will be provided.
Several novel circuits of the rapid single-flux-quantum (RSFQ) family of Josephson-junction digital devices have been designed, fabricated using a 2.5- mu m 1000-A/cm/sup 2/ Nb trilayer technology, and tested at low frequencies. Numerical simulation and measurements have shown that these circuits have considerably wider parameter margins, due to application of several novel design methods. The authors have also carried out an experiment to measure the rate of errors in a simple RSFQ circuit including an inverter, confluence buffer, and Josephson transmission line. Near the middle of the parameter window at 4.2 K, the error probability was definitely lower than 3*10/sup -15/ per logic operation, despite experimentation with rudimentary shielding and filtering.>
Superconducting digital pulse-conserving logic and Josephson static random access memory (JSRAM) memory together enable scalable circuits with energy efficiency 100× beyond leading-node CMOS. Circuit designs support high throughput and low latency when implemented in an advanced fabrication stack with high-critical-current-density Josephson junctions of 1000 μA/μm2. Pulse-conserving logic produces one single-flux-quantum output for each input and includes a three-input, three-output gate producing logical or3, majority3, and and3. Gate macros using dual-rail data encoding eliminate inversion latency and produce efficient implementations of all standard logic functions. A full adder using 70 Josephson junctions has a carry-out latency of 5 ps corresponding to an effective 12 levels of logic at 30 GHz. JSRAM memory uses single-flux-quantum signals throughout an active array to achieve throughput at the same clock rate as the logic. The unit cell has eight Josephson junctions, a signal propagation latency of 1 ps, and a footprint of 2 μm2. Projected density of JSRAM is 4 MB/cm2, and computational density of pulse-conserving logic is on par with leading node CMOS accounting for power densities and clock rates.
The authors argue that superconducting digital electronics is the future trend for high-speed and low-power applications. Low-T/sub c/ technology based on stable Nb-AlO/sub x/-Nb tunneling junctions has been successful in constructing most of the digital circuit logic elements. A four-stage shift register constructed with latching logic operated up to 4 GHz with a power consumption of about 60 mu W per gate. A 12-b analog-digital coverter constructed with a single flux quantum (SFQ) logic showed proper operation with the total power dissipated being only about 100 mu W. Fabrication of Josephson tunneling junctions with high-T/sub c/ materials has been tougher than with low-T/sub c/ materials. However, recently developed very high speed rapid single flux quantum (RSFQ) logic circuits can be applied to weak link type junctions fabricated with YBa/sub 2/Cu/sub 3/O/sub 7-x/ films. Simulations of the various circuits with weak link type junctions, e.g., shift registers, analog-digital converters, etc., show fast operation and reasonable margins. Applications of similar concepts can be applied to NbN circuits operating at above 10 K.>
The potential of a new technology, based on the superconducting Josephson tunneling effect, has been assessed for use in high-speed computer systems. Josephson tunneling circuits for memory and logic functions can be switched at sub-nanosecond delay, do not require standby power, and dissipate extremely low energy, typically less than 10-13joule during fast switching operation. High-speed circuits with high packing densities, not limited by power dissipation problems, can therefore be expected. Low thermal noise at cryogenic temperatures ensures reliable operation despite the low energy switching signal. Practically lossless signal transmission via superconducting lines can be exploited for high-speed operation even when sizeable memory and logic modules are assembled. Two random access memory modules have been designed on the basis of single device experiments. Operational characteristics leading to the conclusion that 30 Mbit capacity, less than 1 watt refrigeration requirement (at 3.6° K) and cycle times of 40 ns (in one case) and 15 ns (in the second case), can be achieved are presented.