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IEEE Transactions on Circuits and Systems

Design of a fast variable-frequency Josephson shift register

V. Nandakumar, T. Van Duzer

Published Jan 1, 1988• 7 citations
Publisher

Abstract

The design of a very-high-speed Josephson junction shift register is presented. Computer simulations show that the circuit can be operated with a two-phase sinusoidal clock at frequencies over 60 GHz. The shift register is based on using nonlatching superconducting interferometric switches to shift a bias current between arms of superconducting loops. The operating margins of the circuit are discussed.>

DOI
10.1109/31.7581

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The design of a very-high-speed Josephson junction shift register is presented. Computer simulations show that the circuit can be operated with a two-phase sinusoidal clock at frequencies over 60 GHz. The shift register is based on using nonlatching superconducting interferometric switches to shift a bias current between arms of superconducting loops. The operating margins of the circuit are discussed.>
A Josephson SFQ (single flux quantum) shift register circuit operating under a two-phase power was designed and tested. The test cell was fabricated using the Nb/AlO/sub x//Nb junction SNEAP process. The main data latch is DC biased; the data storage is accomplished by the transfer of a single flux quantum in or out of a SQUID (superconducting quantum interference device) superconducting loop. A two-phase sinusoidal clock with offset is used to operate the circuit. Simulations verify that the operating frequency can go beyond 70 GHz, with operating margins exceeding 20%. Preliminary measurements indicate that the circuit operates as intended.>
A review of Josephson shift-register circuits that have been designed, fabricated, or tested is presented with emphasis on work in the 1980s. Operating speed is most important, since it often limits system performance. Older designs used square-wave clocks, but most modern designs use offset sine waves, with either two or three phases. Operating margins and gate bias uniformity are key concerns. The fastest measured Josephson shift register operated at 2.3 GHz, which compares well with a GaAs shift register that consumes 250 times more power. The difficulties of high-speed testing have prevented many Josephson shift registers from being operated at their highest speeds. Computer simulations suggest that 30-GHz operation is possible with current Nb/Al/sub 2/O/sub 3//Nb technology. Junctions with critical current densities near 10 kA/cm/sup 2/ would make 100-GHz shift registers feasible.>
The author presents the design and test results for a novel, buffered RSFQ shift register. The register design makes it possible to build a circular 64-b shift register which is insensitive to the clock pulse direction within the experimentally measured DC bias margin of +or-15%. The implementation of a large variety of unidirectional shift registers using either a buffered or a two-Josephson-junction cell design confirms an expected wide DC bias margin of +or-30% (for a 32-b) and high speed, up to 60 GHz (for a 4-b register). Among these circuits is a 256-b shift register. To the author's knowledge, this is the largest RSFQ circuit (533 junctions) reported to date. This shift register was tested to have a DC bias margin of +or-6% and proper high-speed operation up to 12 GHz.>
Experimental superconducting shift registers consisting of on-chip clock generators, clock regeneration and distribution circuits, shift register elements, and readout circuits are designed using rapid single flux quantum logic/memory (RSFQ) gates. A 7-b shift register has been tested to 12 GHz and a 17-b to 21 GHz using external triggering clocks with relative delay measurements. Testing with internal clocks generated from Josephson oscillations shows a potential high-speed operation of 45 GHz for the 7-b and 30 GHz for the 17-b shift registers. Two types of magnetically coupled readout gates are discussed. The chips are fabricated using a Nb/AlO/sub /x/Nb Josephson-junction process at a critical-current density of 1000 A/cm/sup 2/. The power dissipation per bit is 3 mu W.>
Integrated circuit chips were designed and fabricated, based on a Josephson shift register circuit that simulated operation at 25 GHz using the SPICE program. The 6.25-mm/sup 2/ chip featured a twelve-gate, four-stage shift register fabricated with Nb/AlO/sub x//Nb Josephson junctions with a design value of 2000 A/cm/sup 2/ critical current density. SUPERCOMPACT, a general program for the design of monolithic microwave integrated circuits, was used to model the effects of layout geometry on the uniformity and phase coherence of logic gate bias currents. A layout geometry for the superconductive transmission lines and thin-film bias resistors was developed. The original SPICE-designed circuit was modified as a result of these calculations. Modeling indicated that bias current variations could be limited to 3% for all possible logic states of the shift register, and phase coherence of the gates could be maintained to within 2 degrees at 10 GHz. The fundamental soundness of the circuit design was demonstrated by the proper operation of fabricated shift registers.>