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IEEE Transactions on Applied Superconductivity

RSFQ pseudo random generator and its possible applications

Anna Kidiyarova-Shevchenko, Dmitry Y. Zinoviev

Published Jun 1, 1995• 29 citations
Publisher

Abstract

We have analyzed theoretically and simulated a set of 4-bit RSFQ-logic-based Pseudo Random Generators (PRG). These circuits have been fabricated using low-T/sub c/ niobium technology. We have also investigated experimentally an XOR cell and a shift register with parallel outputs that have been used as compound parts of the PRGs. Experimentally measured margins for DC power supply voltage for a PRG with a serial output, an XOR cell and shift register were 10%, 15%, and 15% respectively. In this paper we discuss various possible applications of a PRG in testing RSFQ circuits and also as a source of "quasiwhite" digital noise.>

DOI
10.1109/77.403178

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We have analyzed theoretically and simulated a set of 4-bit RSFQ-logic-based Pseudo Random Generators (PRG). These circuits have been fabricated using low-T/sub c/ niobium technology. We have also investigated experimentally an XOR cell and a shift register with parallel outputs that have been used as compound parts of the PRGs. Experimentally measured margins for DC power supply voltage for a PRG with a serial output, an XOR cell and shift register were 10%, 15%, and 15% respectively. In this paper we discuss various possible applications of a PRG in testing RSFQ circuits and also as a source of "quasiwhite" digital noise.>
This paper describes the design, analysis and test results for a 4-bit pseudo-random bit-sequence generator (PRBSG) implemented with complementary output switching logic (COSL) gates. The PRBSG was optimized using a Monte Carlo simulation method for 10-GHz operation. The circuit has been fabricated using niobium technology with critical current density of 1 kA/cm/sup 2/ and sheet resistance of 1 /spl Omega//sq. The 4-bit PRBSG consists of 12 gates and its area is 1530/spl times/950 /spl mu/m/sup 2/. It has been fully tested with a three-phase power supply, and its power consumption is 0.15 mW. The correct operations have been verified experimentally at clock frequencies of up to 2 GHz.
Shift registers operated in digital feedback mode and utilized as pseudo random noise generators are very attractive for application as noise standards in rf noise power metrology. The paper reports on the concept of the integrated circuits required, based on superconducting Rapid-Single-Flux-Quantum (RSFQ) logic, and realized in Nb/Al/sub 2/O/sub 3/-Al/Nb technology. The design and layout of an 8-bit shift register is presented. Measurement results are reported which prove correct functionality for clock frequencies up to 45 GHz for standard operation. Typical bias current margins for operation of the shift register are /spl plusmn/27%. Further narrow-band limited ranges of operation have been found up to 60 GHz.
A set of tri-stable RSFQ cells has been designed, simulated, fabricated in Hypres, Inc. using 1 kA/cm/sup 2/ low-T/sub c/ Niobium technology and successfully tested. The elements (including a generic X cell, XOR and inverted XOR cells) are fully compatible with binary RSFQ circuits and do not require any input/output conversion. Their use provides an effective way to simplify some complex functional RSFQ blocks. We also describe a novel automated setup for testing of digital superconductive devices which has been used for experimental study of the cells.>
We are introducing a new subfamily of rapid single-flux-quantum (RSFQ) digital cells, based on a single B flip-flop template. The template can be considered as an SFQ flip-flop with up to 4 inputs and 6 outputs. Each input SFQ pulse can change the flip-flop's internal state. Each output presents (in the form of SFQ pulses a specific logic function of the initial state of the cell and input signals. Simple connection of various inputs and/or outputs, combined with shortening or opening of certain branches of the template allows one to implement a variety of RSFQ cells with wide margins. Of these various RSFQ cells, we have designed and successfully tested the T1 cell (asynchronous toggle flip-flop with synchronous destructive readout), single-bit full adder, and single-bit stage of an up-down counter. Experimentally measured margins for dc power supply voltage for these circuits were /spl plusmn/24%, /spl plusmn/24%, and /spl plusmn/17%, respectively.>
We describe the operation of a rapid-single-flux-quantum (RSFQ) hardware random number generator comprising two Josephson oscillators, an XOR gate, and a non-destructive read-out (NDRO) cell. Single-flux-quantum (SFQ) pulse trains fed to the input terminals of the XOR gate contain timing jitters due to thermal noises. Then, the output of the XOR gate becomes random, which is stored in the NDRO cell and fetched by the trigger signal. We experimentally evaluated the output randomness of a test circuit fabricated using a 10 kA/cm2 Nb/AlOx/Nb integration process. For evaluation, the NIST FIPS 140-2 test suite was used. 24 random number sequences of 20 kb length were acquired with the trigger signal of 1 MHz, and evaluated for each operation condition. Relationships between the output randomness and operation conditions were obtained. In addition, numerical simulation demonstrated true random number generation at 20 GHz.