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IEEE Transactions on Applied Superconductivity

Novel tri-stable elements for binary RSFQ circuitry

Dmitry Y. Zinoviev, Oleg A. Mukhanov

Published Jun 1, 1995• 3 citations
Publisher

Abstract

A set of tri-stable RSFQ cells has been designed, simulated, fabricated in Hypres, Inc. using 1 kA/cm/sup 2/ low-T/sub c/ Niobium technology and successfully tested. The elements (including a generic X cell, XOR and inverted XOR cells) are fully compatible with binary RSFQ circuits and do not require any input/output conversion. Their use provides an effective way to simplify some complex functional RSFQ blocks. We also describe a novel automated setup for testing of digital superconductive devices which has been used for experimental study of the cells.>

DOI
10.1109/77.403219

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IEEE Transactions on Applied Superconductivity•Jun 1, 1997•25 citations
A set of tri-stable RSFQ cells has been designed, simulated, fabricated in Hypres, Inc. using 1 kA/cm/sup 2/ low-T/sub c/ Niobium technology and successfully tested. The elements (including a generic X cell, XOR and inverted XOR cells) are fully compatible with binary RSFQ circuits and do not require any input/output conversion. Their use provides an effective way to simplify some complex functional RSFQ blocks. We also describe a novel automated setup for testing of digital superconductive devices which has been used for experimental study of the cells.>
ENGLISH ABSTRACT: Rapid Single Flux Quantum (RSFQ) cells are key in the design of complex and applicable RSFQ electronic circuits. These cells are low-level circuit elements that are used repeatedly to build larger, applicable RSFQ circuitry. Making these cells simple to layout and manufacture, but reliable for extensive use demands a careful development process for RSFQ cells. Cell functionality is verified through simulations, thereafter the cell is laid out in special software packages. Inductance of on-chip superconductor structures is extracted through careful modelling with numerical field solver software. A cell library has been developed by incorporating existing or published cells after further analysis and optimization, as well as developing new cells. Cells that have been adapted into the library include the Josephson transmission line (JTL), Splitter, Merger, D-Flip Flop (DFF), T-Flip Flop (TFF), NOT, AND, OR and XOR, DC-SFQ and SFQ-DC and PTL Driver and Receivers. New cells include NOR, NAND and XNOR. The cells were designed for the IPHT’s RSFQ1D 1kA/cmª and Hypres’ 4.5kA/cmª processes. The cells in the library have good bias current operating margins obtained through simulations (> ±26%). All cells have all the parameters listed in the thesis including extracted inductance values. In order to have a complete and verified RSFQ cell library, cells have been sent for fabrication at IPHT and Hypres facilities. These cells can now be tested on-chip, in the laboratory, to establish functionality and practical bias current margins. All test signal patterns and bias currents required for testing are defined to allow co-workers or collaborators to test the cells.
We have proposed a cell-based design approach for rapid single flux quantum (RSFQ) logic circuits. In our design approach, a binary decision diagram (BDD) is used for representation of logical functions in order to reduce the number of gates. We have made a standard cell library, which is composed of only five basic cells. We add one-junction Josephson transmission line (JTL) to the edge of the input and the output node of some basic cells, by which no deterioration of the DC bias margin is observed for the connection of each cell. In the layout level, the size and the position of the input/output node of each cell are equalized. The standard cell circuits were fabricated by NEC 2.5 kA/cm/sup 2/ and Hypres 1.0 kA/cm/sup 2/ Nb standard process and they were tested at low speed.
Several novel circuits of the rapid single-flux-quantum (RSFQ) family of Josephson-junction digital devices have been designed, fabricated using a 2.5- mu m 1000-A/cm/sup 2/ Nb trilayer technology, and tested at low frequencies. Numerical simulation and measurements have shown that these circuits have considerably wider parameter margins, due to application of several novel design methods. The authors have also carried out an experiment to measure the rate of errors in a simple RSFQ circuit including an inverter, confluence buffer, and Josephson transmission line. Near the middle of the parameter window at 4.2 K, the error probability was definitely lower than 3*10/sup -15/ per logic operation, despite experimentation with rudimentary shielding and filtering.>
We have analyzed theoretically and simulated a set of 4-bit RSFQ-logic-based Pseudo Random Generators (PRG). These circuits have been fabricated using low-T/sub c/ niobium technology. We have also investigated experimentally an XOR cell and a shift register with parallel outputs that have been used as compound parts of the PRGs. Experimentally measured margins for DC power supply voltage for a PRG with a serial output, an XOR cell and shift register were 10%, 15%, and 15% respectively. In this paper we discuss various possible applications of a PRG in testing RSFQ circuits and also as a source of "quasiwhite" digital noise.>
We have designed and RSFQ multiplier-accumulator, the central component of our decimation digital filter. The circuit consists of 38 synchronous RSFQ cells of six types arranged into a rectangular systolic array fed by one parallel input and one serial input. Timing is based on counter-flow clock distribution scheme with simulated maximum clock frequency of 11 GHz. The circuit, fabricated at Hypres, Inc., contains 1100 Josephson junctions, has power consumption less than 0.2 mW, and area less than 2.5 mm/sup 2/. The multiplier-accumulator has been tested at low frequency demonstrating full functionality and stable operation over a 24 hour testing period. This four-bit multiplier accumulator is one of the largest reported RSFQ circuits verified experimentally to date.
We have designed, fabricated, and successfully tested a Time-to-Digital converter (TDC). The TDC circuit consists of superconductive counters based on toggle flip-flops with destructive readout, shift registers, parallel-to-serial converters, and pulse detectors. The value of the counter is latched while the counter is operating at full speed. The TDC resolution is directly determined by the maximum counter speed, or 50 ps for an available 20 GHz clock rate. The circuits are implemented in HYPRES' standard Nb process with a critical current density of 1.0 kA/cm/sup 2/ using HYPRES' library of standard RSFQ cells.