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Superconductor Science and Technology

Design and experimentation of BSFQ logic devices

T. Hosoki, Hiroki Kodaka, M Kitagawa, Yoji Okabe

Published Nov 1, 1999• 3 citations
Publisher

Abstract

Rapid single flux quantum (RSFQ) logic needs synchronous pulses for each gate, so the clock-wiring problem is more serious when designing larger scale circuits with this logic. So we have proposed a new SFQ logic which follows Boolean algebra perfectly by using set and reset pulses. With this logic, the level information of current input is transmitted with these pulses generated by level-to-pulse converters, and each gate calculates logic using its phase level made by these pulses. Therefore, our logic needs no clock in each gate. We called this logic `Boolean SFQ (BSFQ) logic'. In this paper, we report design and experimentation for an AND gate with inverting input based on BSFQ logic. The experimental results for OR and XOR gates are also reported.

DOI
10.1088/0953-2048/12/11/324

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Rapid single flux quantum (RSFQ) logic needs synchronous pulses for each gate, so the clock-wiring problem is more serious when designing larger scale circuits with this logic. So we have proposed a new SFQ logic which follows Boolean algebra perfectly by using set and reset pulses. With this logic, the level information of current input is transmitted with these pulses generated by level-to-pulse converters, and each gate calculates logic using its phase level made by these pulses. Therefore, our logic needs no clock in each gate. We called this logic `Boolean SFQ (BSFQ) logic'. In this paper, we report design and experimentation for an AND gate with inverting input based on BSFQ logic. The experimental results for OR and XOR gates are also reported.
We propose new logic circuits based on Single Flux Quantum logic with Resettable Latch (SFQ-RL). This new logic enables us to initialize the whole circuit and realize an inverter easily. This initialization function is needed for general state machines, in addition, suppressing the failed operation caused by a trapped flux in storage loops. SFQ-RL logic consists of three primitives of gates, "Latch (L)-gate", "Copy(C)-gate" and "OR (O)-gate". L-gate is a kind of flip-flop gate. The difference from a conventional RSFQ latch, "RS-FF" is that L-gate can be reset without emitting an output pulse using "Initialize" pulse. Our numerical simulation shows that the bias margin of L-gate is /spl plusmn/8%. C-gate and O-gate correspond to "Splitter" and "Confluence Buffer" in RSFQ logic, respectively. Every logic function can be realized by only the three primitives. We confirmed the operations, "AND" and "OR" with reasonable margins and speeds by the numerical calculation. We have experimentally demonstrated the logic function such as OR based on SFQ-RL logic. We confirmed the normal operation of the gate with the bias margin of /spl plusmn/25.9%.
This paper presents a basic circuit concept for pulse-driven asynchronous circuits using superconducting rapid single-flux-quantum (RSFQ) logic gates. Today's computer systems perform using a synchronous clock distributed over the whole system. The distribution of the clock signal becomes more difficult as the clock frequency increases because the wavelength of the clock signal becomes shorter than the system size. One way to solve this problem is to use asynchronous circuits in which all circuits perform their functions only under the law of cause and effect. We propose an implementation of the basic asynchronous circuit performing OR/AND logic operations between SFQ pulses. The operations are confirmed by SPICE simulation. We will show a design method for combinational circuits using the proposed basic circuits.
The authors have optimized the design and calculated the margins for a number of single flux quantum (SFQ) logic elements, including AND, OR, XOR, splitter, DC-to-SFQ converter, and SFQ-to-DC converter. These are the fundamental building blocks necessary to construct more complex logic functions such as the half adder and full adder. Experimental tests of the primary gates, the AND, OR, XOR, and splitter, tests were made by imbedding each test gate between DC-to-SFQ converters at the inputs and SFQ-to-DC converters at the outputs. Automated testing of each circuit was used to determine functionality, optimum bias levels, and margins. The experimental bias current margins for each gate are consistent with the simulations.>
Rapid single flux quantum (RSFQ) logic is a digital circuit technology that in recent years has presented itself as an alternative to semiconductors in the application of ultra high speed, very low power applications. The optimal timing of digital circuits operating at hundreds of GHz is still a complex problem for both RSFQ and semiconductor technologies. The fact that most RSFQ gates require a clock signal to function makes this even more complex. Various RSFQ timing schemes have been adapted from semiconductor design methodologies, and some have been designed specifically for RSFQ. Currently, synchronous clocking schemes outperform other schemes, but with the scale of RSFQ circuits ever increasing, the proper use of timing schemes are becoming more crucial. This paper describes a new asynchronous self-timing scheme where the details of clock distribution and clocking are built into the logic gates. Tests were done on the newly developed asynchronous logic gates and an asynchronous full adder was implemented and tested
We propose an asynchronous single flux quantum (SFQ) logic gate composed of a conventional clocked logic gate and an input signal merger that generates a self-clock for the clocked logic gate. By using this self-clocking, we can design any 0-preserving logic gate, including exclusive OR (XOR). The proposed asynchronous SFQ logic gates have adjustable allowable input skew by varying the delay between the merger and internal clock input for the clocked logic gate. We design and evaluate the asynchronous AND, OR, and XOR gates that have an allowable input skew of approximately 8 ps assuming the use of the 10 kA/cm2Nb fabrication process using the proposed design method. We experimentally confirm the correct operation of the asynchronous SFQ XOR gate. We design a completely asynchronous 4-bit-input carry-lookahead adder (CLA) using the designed asynchronous gates. We found that the circuit area and number of Josephson junctions required to design a 4-bit-input CLA can be reduced by > 50% compared to that of the synchronous concurrent-flow 4-bit-input CLA without deterioration of the throughput.
Rapid Single Flux Quantum (RSFQ) logic is a digital circuit technology that in recent years has presented itself as an alternative to semiconductors in the application of ultra high speed, very low power applications. The optimal timing of digital circuits operating at hundreds of Gigahertz is still a complex problem for both RSFQ and semiconductor technologies. The fact that most RSFQ gates require a clock signal to function makes this even more complex. Various RSFQ liming schemes have been adapted from semiconductor design methodologies, and some have been designed specifically for RSFQ. Currently, synchronous clocking schemes outperform other schemes, but with the scale of RSFQ circuits ever increasing, the proper use of timing schemes are becoming more crucial. This paper describes a new asynchronous self-timing scheme where the details of clock distribution and clocking are built into the logic gates. Tests were done on the newly developed asynchronous logic-gales and a asynchronous full adder was implemented and tested.