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International Conference on Advances in Computing, Communications and Informatics (ICACCI)

Performance evaluation of regular cycle non-binary LDPC codes in AWGN channel

Ameenudeen Pe, Anchare V. Babu

Published Aug 3, 2012• 0 citations
Publisher

Abstract

Low Density Parity Check Codes (LDPC) are a group of channel codes which can be decoded using a graph. LDPC codes are known to give near Shannon limit performance in Additive White Gaussian Channel (AWGN), but for large block-lengths and irregular construction. To overcome this limitation, it has been proposed to define codes over a higher order Galois Field. In this paper,we construct a regular cycle non binary LDPC code over GF(q), where q=2p.We use a Fast Fourier Transform (FFT) based low complexity algorithm to decode the LDPC code defined over a large Galois Field. We evaluate the performance of these codes in AWGN channel using computer simulations and show that they are giving excellent BER performance.

DOI
10.1145/2345396.2345600

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Low Density Parity Check Codes (LDPC) are a group of channel codes which can be decoded using a graph. LDPC codes are known to give near Shannon limit performance in Additive White Gaussian Channel (AWGN), but for large block-lengths and irregular construction. To overcome this limitation, it has been proposed to define codes over a higher order Galois Field. In this paper,we construct a regular cycle non binary LDPC code over GF(q), where q=2p.We use a Fast Fourier Transform (FFT) based low complexity algorithm to decode the LDPC code defined over a large Galois Field. We evaluate the performance of these codes in AWGN channel using computer simulations and show that they are giving excellent BER performance.
Low-density parity check (LDPC) codes are known to perform well in the presence of additive white Gaussian noise (AWGN) but for very large block lengths. It has been proposed to define the codes over high order Galois fields to overcome this limitation. In this paper we construct new quasi-cyclic non-binary LDPC codes with moderate code lengths from Reed-Solomon codes with two message symbols proposed by Lin et al defined over large finite fields. We evaluate the performance of these codes on the AWGN channel by computer simulation and show that they outperform binary LDPC codes of the same length in binary bits.
Low Density Parity Check (LDPC) codes have excellent error correcting performance. LDPC codes are one of the block coding techniques and it performs near Shannon limit and recommended for many practical applications. Non-binary LDPC codes extension of binary LDPC in error correcting property especially for short and moderate block length. In many digital communication systems these codes have strong competitors of turbo codes for error control. Low Density Parity Check as it name is suggests that in a parity check matrix (H) consists of very small number of non-zero elements comparing with zero elements. The strength of the LDPC code defines Parity Check Matrix (PCM). LDPC code contains two types of decoding algorithms hard and soft decision algorithm. By comparing with other traditional decoding algorithm FFT based sum product algorithm reduced computation complexity with better decoding performance. In this paper, LDPC codes for FFT based sum product decoding algorithm performances are analysed for various order of Galois Field GF(q) using AWGN channel. Decoding performance measured in terms of symbol error rate which improve with increasing order of Galois field.
Low Density Parity Check (LDPC) codes are one of the block coding techniques that can approach the Shannon’s limit within a fraction of a decibel for high block lengths. In many digital communication systems these codes have strong competitors of turbo codes for error control. LDPC codes performance depends on the excellent design of parity check matrix and many diverse research methods have been used by different study groups to evaluate the performance. In this research work finite fields construction method is used and diverse techniques like masking, dispersion and array dispersion for the construction of parity check matrix H. These constructed codes are then simulated to make the performance evaluation. The key interest of this research work was to inspect the performance of LDPC codes based on finite fields. A comprehensive masking technique was also an objective of this research work. Simulation was done for different rates using additive white Gaussian noise (AWGN) channel. In MATLAB a library of different functions was created to perform the task for base matrix construction, dispersion, masking, generator matrix construction etc. Results give an idea that even at BER of 10-6 these short length LDPC codes performed much better and have no error floor. BER curves are also with 2-3dB from Shannon’s limit at BER of 10-6 for different rates.
In this paper, we are concerned with the finite-length analysis of low-density parity-check (LDPC) codes when used over additive white Gaussian noise (AWGN) channels. We present the iterative decoding algorithm of LDPC codes, and we also discuss the encoding methods and the bipartite graph representation of LDPC codes ensemble. Finite-length LDPC code performances are investigated, and the influence of cycle is pointed out. Simulation results show that irregular LDPC codes with variable and check node degree distribution optimized for infinite-length codes are not optimal for finite-length LDPC codes, and the error patterns of both regular and irregular codes are investigated as an effort to improve the performance and design methodology of finite-length LDPC codes.
The concept of Low Density Parity Check (LDPC) coding over Galois Fields GF (q = 2p) is a generalization of the industry standard binary LDPC coding. The performance for short block length codes is significantly higher for non-binary codes (over higher order GF fields), but on the other hand, the decoding complexity is increased. Therefore the hardware implementation of a decoder is still a challenging task. Most of the few implementations known from the literature use multiplierless computing units. In this article we present a different approach that does not exclude multiplier blocks from the decoder module. This approach is specifically intended for FPGA (Field Programmable Gate Array) implementation. We propose the decoding algorithm formulation that uses multiplications in the computation step of the Check Nodes and summations performed in the Bit Nodes. The main reason is to enable mapping a part of the algorithm to the multiplier cores available in the FPGA devices. In the article we present the decoder structure that has been developed and the construction of its building blocks. We also provide synthesis results for the Xilinx FPGAs and simulation results for a simple BPSK (Binary Phase Shift Keying) modulation model over AWGN (Additive White Gaussian Noise) channel.
Binary low density parity check (LDPC) codes have been shown to have near Shannon limit performance when decoded using a probabilistic decoding algorithm. The analogous codes defined over finite fields GF(q) of order q>2 show significantly improved performance. We present the results of Monte Carlo simulations of the decoding of infinite LDPC codes which can be used to obtain good constructions for finite codes. We also present empirical results for the Gaussian channel including a rate 1/4 code with bit error probability of 10/sup -4/ at E/sub b//N/sub 0/=-0.05 dB.