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IEEE Consumer Communications and Networking Conference

GF(q) LDPC decoder design for FPGA implementation

Wojciech Sułek, Marcin Kucharczyk, Grzegorz Dziwoki

Published Jan 1, 2013• 14 citations
Publisher

Abstract

The concept of Low Density Parity Check (LDPC) coding over Galois Fields GF (q = 2p) is a generalization of the industry standard binary LDPC coding. The performance for short block length codes is significantly higher for non-binary codes (over higher order GF fields), but on the other hand, the decoding complexity is increased. Therefore the hardware implementation of a decoder is still a challenging task. Most of the few implementations known from the literature use multiplierless computing units. In this article we present a different approach that does not exclude multiplier blocks from the decoder module. This approach is specifically intended for FPGA (Field Programmable Gate Array) implementation. We propose the decoding algorithm formulation that uses multiplications in the computation step of the Check Nodes and summations performed in the Bit Nodes. The main reason is to enable mapping a part of the algorithm to the multiplier cores available in the FPGA devices. In the article we present the decoder structure that has been developed and the construction of its building blocks. We also provide synthesis results for the Xilinx FPGAs and simulation results for a simple BPSK (Binary Phase Shift Keying) modulation model over AWGN (Additive White Gaussian Noise) channel.

DOI
10.1109/ccnc.2013.6488484

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The concept of Low Density Parity Check (LDPC) coding over Galois Fields GF (q = 2p) is a generalization of the industry standard binary LDPC coding. The performance for short block length codes is significantly higher for non-binary codes (over higher order GF fields), but on the other hand, the decoding complexity is increased. Therefore the hardware implementation of a decoder is still a challenging task. Most of the few implementations known from the literature use multiplierless computing units. In this article we present a different approach that does not exclude multiplier blocks from the decoder module. This approach is specifically intended for FPGA (Field Programmable Gate Array) implementation. We propose the decoding algorithm formulation that uses multiplications in the computation step of the Check Nodes and summations performed in the Bit Nodes. The main reason is to enable mapping a part of the algorithm to the multiplier cores available in the FPGA devices. In the article we present the decoder structure that has been developed and the construction of its building blocks. We also provide synthesis results for the Xilinx FPGAs and simulation results for a simple BPSK (Binary Phase Shift Keying) modulation model over AWGN (Additive White Gaussian Noise) channel.
The non-binary Low Density Parity Check (LDPC) codes over Galois Fields GF(q = 2 p ) have evolved from the binary LDPC codes that are today an industry standard for channel coding. The performance of short block length codes is significantly higher for non-binary LDPC, at the cost of increased decoding complexity. The efficient decoder hardware implementation is still a challenging task. Most of the recently proposed hardware realizations are ASIC-oriented as they employ multiplierless computation units. This article concerns a different decoder design approach that is specifically intended for an FPGA implementation. The reformulated mixed-domain FFT-BP decoding algorithm is applied that does not exclude the multiplication units. This allows mapping a part of the algorithm to the multiplier cores embedded in an FPGA. In this article we concentrate on the important issue of the proper selection of the numeric precision employed. We present the partially parallel extension of the mixed-domain decoder that operates for the structured codes. Then we carefully analyze the finite precision effects on the decoding performance. By simulation and synthesis results we show that it is advantageous to segment the decoder dataflow into 3 parts with different precision. The provided results also facilitate the precision selection for maximum performance or for some performance- complexity tradeoff. Index Terms—Error correcting codes, LDPC codes, Non- binary codes, Iterative decoder, Hardware decoder
Hardware Implementation of GF(2m){\rm GF}(2^{m})GF(2m) LDPC Decoders
Low density parity check (LDPC) codes over GF(2m) are an extension of binary LDPC codes with significantly higher performance. However, the computational complexity of the encoders/decoders for these codes is also higher. Hence there is a substantial lack of hardware implementations for LDPC over GF(2m) codes. This paper proposes a novel variation of the belief propagation algorithm for GF(2m) LDPC codes. The new algorithm results in a reduced hardware complexity when implemented in VLSI. The serial architecture of the novel decoding algorithm and two other algorithms for LDPC over GF(2m) are implemented on an FPGA. The results show that the proposed algorithm has substantial advantages over existing methods. We show that the implementation of LDPC over GF(2m) decoder is feasible for short to medium length codes. The additional complexity of the decoder is balanced by the superior performance of GF(2m) LDPC codes.
Forward error correction is an essential part of digital communication systems. Non-binary low-density parity-check (NB-LDPC) codes have an excellent communications performance for short block lengths. The higher the field size is, the better the communications performance is. Non-binary LDPC codes can outperform all other state-of-the-art code classes. However, the algorithmic decoding complexity grows with the field size. For an intended, future use of these codes in real systems, an efficient hardware implementation is mandatory. Hardware architectures for binary LDPC codes are well investigated, but efficient implementation of non-binary LDPC decoders is still an open field. To the best of our knowledge, this paper studies for the first time the hardware implementation costs for non-binary LDPC decoders with Galois field sizes of 4, 16 and 256 on FPGA and a 65nm ASIC technology.
Low Density Parity Check Codes (LDPC) are a group of channel codes which can be decoded using a graph. LDPC codes are known to give near Shannon limit performance in Additive White Gaussian Channel (AWGN), but for large block-lengths and irregular construction. To overcome this limitation, it has been proposed to define codes over a higher order Galois Field. In this paper,we construct a regular cycle non binary LDPC code over GF(q), where q=2p.We use a Fast Fourier Transform (FFT) based low complexity algorithm to decode the LDPC code defined over a large Galois Field. We evaluate the performance of these codes in AWGN channel using computer simulations and show that they are giving excellent BER performance.
Low Density Parity Check (LDPC) codes over GF(2) are an extension of binary LDPC codes with significantly higher performance. However, the computational complexity of the encoders/decoders for these codes is also higher. Hence there is a substantial lack of hardware implementations for LDPC over GF(2) codes. This paper proposes a novel variation of the belief propagation algorithm for GF(2) LDPC codes. The new algorithm results in a reduced hardware complexity when implemented in VLSI. The serial architecture of the novel decoding algorithm and two other algorithms for LDPC over GF(2) are implemented on an FPGA. The results show that the proposed algorithm has substantial advantages over existing methods. We show that the implementation of LDPC over GF(2) decoder is feasible for short to medium length codes. The additional complexity of the decoder is balanced by the superior performance of GF(2) LDPC codes.
Low Density Parity Check (LDPC) codes have excellent error correcting performance. LDPC codes are one of the block coding techniques and it performs near Shannon limit and recommended for many practical applications. Non-binary LDPC codes extension of binary LDPC in error correcting property especially for short and moderate block length. In many digital communication systems these codes have strong competitors of turbo codes for error control. Low Density Parity Check as it name is suggests that in a parity check matrix (H) consists of very small number of non-zero elements comparing with zero elements. The strength of the LDPC code defines Parity Check Matrix (PCM). LDPC code contains two types of decoding algorithms hard and soft decision algorithm. By comparing with other traditional decoding algorithm FFT based sum product algorithm reduced computation complexity with better decoding performance. In this paper, LDPC codes for FFT based sum product decoding algorithm performances are analysed for various order of Galois Field GF(q) using AWGN channel. Decoding performance measured in terms of symbol error rate which improve with increasing order of Galois field.