Challenges
Datasets
Workspaces
Papers
Discussions
Leaderboard
Log inSign up
Challenges
Datasets
Workspaces
Papers
Discussions
Leaderboard
Blog
Job Board
Q3AS

© 2026 Aqora Quantum S.A.S.

TermsPrivacyLegal Notice

IEEE Transactions on Circuits and Systems I Regular Papers

Hardware Implementation of ${\rm GF}(2^{m})$ LDPC Decoders

Christian Spagnol, Emmanuel Popovici, William Peter Marnane

Published Mar 10, 2009• 69 citations
Publisher

Abstract

Low density parity check (LDPC) codes over GF(2m) are an extension of binary LDPC codes with significantly higher performance. However, the computational complexity of the encoders/decoders for these codes is also higher. Hence there is a substantial lack of hardware implementations for LDPC over GF(2m) codes. This paper proposes a novel variation of the belief propagation algorithm for GF(2m) LDPC codes. The new algorithm results in a reduced hardware complexity when implemented in VLSI. The serial architecture of the novel decoding algorithm and two other algorithms for LDPC over GF(2m) are implemented on an FPGA. The results show that the proposed algorithm has substantial advantages over existing methods. We show that the implementation of LDPC over GF(2m) decoder is feasible for short to medium length codes. The additional complexity of the decoder is balanced by the superior performance of GF(2m) LDPC codes.

DOI
10.1109/tcsi.2009.2016621

Related papers

Hardware Implementation of GF(2 m ) LDPC Decoders.

Christian Spagnol, Emanuel Mihai Popovici, William Peter Marnane

Low Density Parity Check (LDPC) codes over GF(2) are an extension of binary LDPC codes with significantly higher performance. However, the computational complexity of the encoders/decoders for these codes is also higher. Hence there is a substantial lack of hardware implementations for LDPC over GF(2) codes. This paper proposes a novel variation of the belief propagation algorithm for GF(2) LDPC codes. The new algorithm results in a reduced hardware complexity when implemented in VLSI. The serial architecture of the novel decoding algorithm and two other algorithms for LDPC over GF(2) are implemented on an FPGA. The results show that the proposed algorithm has substantial advantages over existing methods. We show that the implementation of LDPC over GF(2) decoder is feasible for short to medium length codes. The additional complexity of the decoder is balanced by the superior performance of GF(2) LDPC codes.

IEEE Transactions on Circuits and Systems•Jan 1, 2009•47 citations

Hardware Implementation of LDPC Decoders

Christian Spagnol, Emanuel Mihai Popovici, William Peter Marnane

Low density parity check (LDPC) codes over are an extension of binary LDPC codes with significantly higher performance. However, the computational complexity of the encoders/decoders for these codes is also higher. Hence there is a substantial lack of hardware implementations for LDPC over codes. This paper proposes a novel variation of the belief propagation algorithm for LDPC codes. The new algorithm results in a reduced hardware complexity when imple- mented in VLSI. The serial architecture of the novel decoding algorithm and two other algorithms for LDPC over are implemented on an FPGA. The results show that the proposed algorithm has substantial advantages over existing methods. We show that the implementation of LDPC over decoder is feasible for short to medium length codes. The additional com- plexity of the decoder is balanced by the superior performance of LDPC codes.

•Jan 1, 2009•6 citations

GF(q) LDPC decoder design for FPGA implementation

Wojciech Sułek, Marcin Kucharczyk, Grzegorz Dziwoki

The concept of Low Density Parity Check (LDPC) coding over Galois Fields GF (q = 2p) is a generalization of the industry standard binary LDPC coding. The performance for short block length codes is significantly higher for non-binary codes (over higher order GF fields), but on the other hand, the decoding complexity is increased. Therefore the hardware implementation of a decoder is still a challenging task. Most of the few implementations known from the literature use multiplierless computing units. In this article we present a different approach that does not exclude multiplier blocks from the decoder module. This approach is specifically intended for FPGA (Field Programmable Gate Array) implementation. We propose the decoding algorithm formulation that uses multiplications in the computation step of the Check Nodes and summations performed in the Bit Nodes. The main reason is to enable mapping a part of the algorithm to the multiplier cores available in the FPGA devices. In the article we present the decoder structure that has been developed and the construction of its building blocks. We also provide synthesis results for the Xilinx FPGAs and simulation results for a simple BPSK (Binary Phase Shift Keying) modulation model over AWGN (Additive White Gaussian Noise) channel.

IEEE Consumer Communications and Networking Conference•Jan 1, 2013•14 citations

Reduced complexity and improved performance decoding algorithm for nonbinary LDPC codes over GF(q)

Xin Chen, Aidong Men

Low-density parity-check (LDPC) codes over finite fields GF(q) have a better performance than those of the binary low-density parity-check codes, at short and medium block lengths, but the decoder of GF(q)-LDPC has more complexity. In this paper, we present a new reduced-complexity belief propagation (BP) decoding algorithm for GF(q)-LDPC codes by analyzing the reliability of code symbols. Instead of update all the variable nodes during iteration, we just update variable nodes which are mostly to be in an error. The algorithm also shows a property to reduce the effects of oscillating on decoding. The simulations prove that we could improve performance and reduce complexity at the same time for short and medium GF(q)-LDPC codes.

IEEE International Conference on Communication Technology (ICCT)•Nov 1, 2008•6 citations

Decoding Algorithms for Nonbinary LDPC Codes Over GF$(q)$

David Declercq, M.P.C. Fossorier

In this letter, we address the problem of decoding nonbinary low-density parity-check (LDPC) codes over finite fields GF(q), with reasonable complexity and good performance. In the first part of the letter, we recall the original belief propagation (BP) decoding algorithm and its Fourier domain implementation. We show that the use of tensor notations for the messages is very convenient for the algorithm description and understanding. In the second part of the letter, we introduce a simplified decoder which is inspired by the min-sum decoder for binary LDPC codes. We called this decoder extended min-sum (EMS). We show that it is possible to greatly reduce the computational complexity of the check-node processing by computing approximate reliability measures with a limited number of values in a message. By choosing appropriate correction factors or offsets, we show that the EMS decoder performance is quite good, and in some cases better than the regular BP decoder. The optimal values of the factor and offset correction are obtained asymptotically with simulated density evolution. Our simulations on ultra-sparse codes over very-high-order fields show that nonbinary LDPC codes are promising for applications which require low frame-error rates for small or moderate codeword lengths. The EMS decoder is a good candidate for practical hardware implementations of such codes

IEEE Transactions on Communications•Apr 1, 2007•724 citations

Decoder FPGA Implementation

Wojciech Sułek

The non-binary Low Density Parity Check (LDPC) codes over Galois Fields GF(q = 2 p ) have evolved from the binary LDPC codes that are today an industry standard for channel coding. The performance of short block length codes is significantly higher for non-binary LDPC, at the cost of increased decoding complexity. The efficient decoder hardware implementation is still a challenging task. Most of the recently proposed hardware realizations are ASIC-oriented as they employ multiplierless computation units. This article concerns a different decoder design approach that is specifically intended for an FPGA implementation. The reformulated mixed-domain FFT-BP decoding algorithm is applied that does not exclude the multiplication units. This allows mapping a part of the algorithm to the multiplier cores embedded in an FPGA. In this article we concentrate on the important issue of the proper selection of the numeric precision employed. We present the partially parallel extension of the mixed-domain decoder that operates for the structured codes. Then we carefully analyze the finite precision effects on the decoding performance. By simulation and synthesis results we show that it is advantageous to segment the decoder dataflow into 3 parts with different precision. The provided results also facilitate the precision selection for maximum performance or for some performance- complexity tradeoff. Index Terms—Error correcting codes, LDPC codes, Non- binary codes, Iterative decoder, Hardware decoder

•Jan 1, 2015•0 citations
Hardware Implementation of GF(2m){\rm GF}(2^{m})GF(2m) LDPC Decoders
Low density parity check (LDPC) codes over GF(2m) are an extension of binary LDPC codes with significantly higher performance. However, the computational complexity of the encoders/decoders for these codes is also higher. Hence there is a substantial lack of hardware implementations for LDPC over GF(2m) codes. This paper proposes a novel variation of the belief propagation algorithm for GF(2m) LDPC codes. The new algorithm results in a reduced hardware complexity when implemented in VLSI. The serial architecture of the novel decoding algorithm and two other algorithms for LDPC over GF(2m) are implemented on an FPGA. The results show that the proposed algorithm has substantial advantages over existing methods. We show that the implementation of LDPC over GF(2m) decoder is feasible for short to medium length codes. The additional complexity of the decoder is balanced by the superior performance of GF(2m) LDPC codes.
Low Density Parity Check (LDPC) codes over GF(2) are an extension of binary LDPC codes with significantly higher performance. However, the computational complexity of the encoders/decoders for these codes is also higher. Hence there is a substantial lack of hardware implementations for LDPC over GF(2) codes. This paper proposes a novel variation of the belief propagation algorithm for GF(2) LDPC codes. The new algorithm results in a reduced hardware complexity when implemented in VLSI. The serial architecture of the novel decoding algorithm and two other algorithms for LDPC over GF(2) are implemented on an FPGA. The results show that the proposed algorithm has substantial advantages over existing methods. We show that the implementation of LDPC over GF(2) decoder is feasible for short to medium length codes. The additional complexity of the decoder is balanced by the superior performance of GF(2) LDPC codes.
Low density parity check (LDPC) codes over are an extension of binary LDPC codes with significantly higher performance. However, the computational complexity of the encoders/decoders for these codes is also higher. Hence there is a substantial lack of hardware implementations for LDPC over codes. This paper proposes a novel variation of the belief propagation algorithm for LDPC codes. The new algorithm results in a reduced hardware complexity when imple- mented in VLSI. The serial architecture of the novel decoding algorithm and two other algorithms for LDPC over are implemented on an FPGA. The results show that the proposed algorithm has substantial advantages over existing methods. We show that the implementation of LDPC over decoder is feasible for short to medium length codes. The additional com- plexity of the decoder is balanced by the superior performance of LDPC codes.
The concept of Low Density Parity Check (LDPC) coding over Galois Fields GF (q = 2p) is a generalization of the industry standard binary LDPC coding. The performance for short block length codes is significantly higher for non-binary codes (over higher order GF fields), but on the other hand, the decoding complexity is increased. Therefore the hardware implementation of a decoder is still a challenging task. Most of the few implementations known from the literature use multiplierless computing units. In this article we present a different approach that does not exclude multiplier blocks from the decoder module. This approach is specifically intended for FPGA (Field Programmable Gate Array) implementation. We propose the decoding algorithm formulation that uses multiplications in the computation step of the Check Nodes and summations performed in the Bit Nodes. The main reason is to enable mapping a part of the algorithm to the multiplier cores available in the FPGA devices. In the article we present the decoder structure that has been developed and the construction of its building blocks. We also provide synthesis results for the Xilinx FPGAs and simulation results for a simple BPSK (Binary Phase Shift Keying) modulation model over AWGN (Additive White Gaussian Noise) channel.
Low-density parity-check (LDPC) codes over finite fields GF(q) have a better performance than those of the binary low-density parity-check codes, at short and medium block lengths, but the decoder of GF(q)-LDPC has more complexity. In this paper, we present a new reduced-complexity belief propagation (BP) decoding algorithm for GF(q)-LDPC codes by analyzing the reliability of code symbols. Instead of update all the variable nodes during iteration, we just update variable nodes which are mostly to be in an error. The algorithm also shows a property to reduce the effects of oscillating on decoding. The simulations prove that we could improve performance and reduce complexity at the same time for short and medium GF(q)-LDPC codes.
Decoding Algorithms for Nonbinary LDPC Codes Over GF(q)(q)(q)
In this letter, we address the problem of decoding nonbinary low-density parity-check (LDPC) codes over finite fields GF(q), with reasonable complexity and good performance. In the first part of the letter, we recall the original belief propagation (BP) decoding algorithm and its Fourier domain implementation. We show that the use of tensor notations for the messages is very convenient for the algorithm description and understanding. In the second part of the letter, we introduce a simplified decoder which is inspired by the min-sum decoder for binary LDPC codes. We called this decoder extended min-sum (EMS). We show that it is possible to greatly reduce the computational complexity of the check-node processing by computing approximate reliability measures with a limited number of values in a message. By choosing appropriate correction factors or offsets, we show that the EMS decoder performance is quite good, and in some cases better than the regular BP decoder. The optimal values of the factor and offset correction are obtained asymptotically with simulated density evolution. Our simulations on ultra-sparse codes over very-high-order fields show that nonbinary LDPC codes are promising for applications which require low frame-error rates for small or moderate codeword lengths. The EMS decoder is a good candidate for practical hardware implementations of such codes
The non-binary Low Density Parity Check (LDPC) codes over Galois Fields GF(q = 2 p ) have evolved from the binary LDPC codes that are today an industry standard for channel coding. The performance of short block length codes is significantly higher for non-binary LDPC, at the cost of increased decoding complexity. The efficient decoder hardware implementation is still a challenging task. Most of the recently proposed hardware realizations are ASIC-oriented as they employ multiplierless computation units. This article concerns a different decoder design approach that is specifically intended for an FPGA implementation. The reformulated mixed-domain FFT-BP decoding algorithm is applied that does not exclude the multiplication units. This allows mapping a part of the algorithm to the multiplier cores embedded in an FPGA. In this article we concentrate on the important issue of the proper selection of the numeric precision employed. We present the partially parallel extension of the mixed-domain decoder that operates for the structured codes. Then we carefully analyze the finite precision effects on the decoding performance. By simulation and synthesis results we show that it is advantageous to segment the decoder dataflow into 3 parts with different precision. The provided results also facilitate the precision selection for maximum performance or for some performance- complexity tradeoff. Index Terms—Error correcting codes, LDPC codes, Non- binary codes, Iterative decoder, Hardware decoder