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IEEE Information Theory Workshop (ITW)

Low density parity check codes over GF(q)

Matthew C. Davey, David Mackay

Published Nov 27, 2002• 182 citations
Publisher

Abstract

Binary low density parity check (LDPC) codes have been shown to have near Shannon limit performance when decoded using a probabilistic decoding algorithm. The analogous codes defined over finite fields GF(q) of order q>2 show significantly improved performance. We present the results of Monte Carlo simulations of the decoding of infinite LDPC codes which can be used to obtain good constructions for finite codes. We also present empirical results for the Gaussian channel including a rate 1/4 code with bit error probability of 10/sup -4/ at E/sub b//N/sub 0/=-0.05 dB.

DOI
10.1109/itw.1998.706440

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Low-density parity-check (LDPC) codes over finite fields GF(q) have a better performance than those of the binary low-density parity-check codes, at short and medium block lengths, but the decoder of GF(q)-LDPC has more complexity. In this paper, we present a new reduced-complexity belief propagation (BP) decoding algorithm for GF(q)-LDPC codes by analyzing the reliability of code symbols. Instead of update all the variable nodes during iteration, we just update variable nodes which are mostly to be in an error. The algorithm also shows a property to reduce the effects of oscillating on decoding. The simulations prove that we could improve performance and reduce complexity at the same time for short and medium GF(q)-LDPC codes.
Low-density parity check (LDPC) codes are known to perform well in the presence of additive white Gaussian noise (AWGN) but for very large block lengths. It has been proposed to define the codes over high order Galois fields to overcome this limitation. In this paper we construct new quasi-cyclic non-binary LDPC codes with moderate code lengths from Reed-Solomon codes with two message symbols proposed by Lin et al defined over large finite fields. We evaluate the performance of these codes on the AWGN channel by computer simulation and show that they outperform binary LDPC codes of the same length in binary bits.
Low Density Parity Check Codes (LDPC) are a group of channel codes which can be decoded using a graph. LDPC codes are known to give near Shannon limit performance in Additive White Gaussian Channel (AWGN), but for large block-lengths and irregular construction. To overcome this limitation, it has been proposed to define codes over a higher order Galois Field. In this paper,we construct a regular cycle non binary LDPC code over GF(q), where q=2p.We use a Fast Fourier Transform (FFT) based low complexity algorithm to decode the LDPC code defined over a large Galois Field. We evaluate the performance of these codes in AWGN channel using computer simulations and show that they are giving excellent BER performance.
After the introduction of iterative coding, Low Density Parity Check (LDPC) codes have received a lot of attention due to their remarkable near Shannon-limit performance and practical decoder implementation. However, when employing an LDPC code for various applications, multiple issues do arise at the simulation, algorithm and implementation levels. The first issue is the performance evaluation of the iterative LDPC decoder in the very low Bit Error Rate (BER) regions. So far, no analytical tool has been developed to evaluate the performance of LDPC codes. Unfortunately standard Monte Carlo (MC) simulations cannot be used for performance estimation in these low BER regions due to prohibitive execution times. The second issue is the efficiency of the decoding algorithm. Due to the presence of short cycles in the bipartite graph, sum-product decoding algorithms lead to considerable performance loss for short block-length LDPC codes and produce error floors for longer codes. In addition, the iterative processing and estimation of soft probabilistic values with these algorithms result in very high computational complexity, which in turn impedes the adoption of LDPC codes for power constrained systems. Another prime objective is to design a high throughput decoder architecture which is capable of supporting multiple rates and variable code lengths within minimal area. This work aims to address and provide solutions to the above problems. As a solution to the performance estimation problem of LDPC codes, a highly efficient and novel fast BER simulation technique is developed. At the algorithm level, a performance improvement and error floor avoidance method is introduced, and a computationally efficient algorithm is developed for the sum-product decoding of LDPC codes. And finally, at the architecture level, a high throughput multi-rate variable code length implementation is presented which, when implemented, efficiently minimizes device resources while alleviating the routing complexity of the decoder.