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International Joint Conference on Computer Science and Software Engineering

Accelerator circuits for quantum simulation

Yuranan Kitrungrotsakul, Prabhas Chongstitvatana

Published Jul 1, 2015• 0 citations
Publisher

Abstract

Although a quantum computer is the future of computing, its practical implementation is still far off. Programming a quantum computer is also difficult. Thus, using a quantum computer simulator is a way to learn how to use a quantum computer. QCL is one of the quantum computer simulators. It can simulate the quantum environment and execute quantum computer programs. However, the quantum computer simulator has limited storage due to its data structure that simulates quantum bits. It takes long time to simulate a large number of quantum bits. This work proposes an accelerator of quantum simulator which is implemented in hardware circuits with Field Programmable Gate Array technology.

DOI
10.1109/jcsse.2015.7219802

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Although a quantum computer is the future of computing, its practical implementation is still far off. Programming a quantum computer is also difficult. Thus, using a quantum computer simulator is a way to learn how to use a quantum computer. QCL is one of the quantum computer simulators. It can simulate the quantum environment and execute quantum computer programs. However, the quantum computer simulator has limited storage due to its data structure that simulates quantum bits. It takes long time to simulate a large number of quantum bits. This work proposes an accelerator of quantum simulator which is implemented in hardware circuits with Field Programmable Gate Array technology.
Currently, the theory of quantum computing is actively developing. Despite the fact that a quantum computer has some features, any algorithm designed for a classical computer can be implemented for a quantum one. The relevance of the topic of quantum computers is confirmed by the fact that even now banking systems, cryptography and encryption of information require enormous resources of computing systems, these are just some examples, but the most important and vivid ones that relate to the everyday life of a huge part of the world's population. A hardware computing core has been developed and simulated, which is the main part of an accelerator based on field-programmable gate array with computer aided design Altera Quartus. Considering the obtained time dependence of the number of cycles required for the impact of a single-qubit quantum gate on a quantum register on the number of qubits and parallel arithmetic logic units in the hardware computing core, when simulating quantum computing, a method was developed to determine the increase in hardware performance and ways to improve the performance of an accelerator based on a hardware computing core were developed. based on field-programmable gate array.
The quantum computer is emerging technology since it can resolve complex tasks such as factorization or search problem faster than classical computers. However, simulation of the quantum computer is difficult because computational load increases exponentially as the number of qubits used in the circuit is increased. This paper proposes a hardware architecture for quantum circuit simulation. To implement simulator smaller, our architecture operates based on a 1-input single gate regardless of the number of qubits used in the circuit In addition, our architecture helps to reduce simulation time by skipping calculation and data transfer. The proposed architecture is implemented on FPGA and the experimental results show that our architecture reduces 79.2% of the multiplication process when we simulate 20-qubit quantum Fourier transform with a small hardware size.
A 16-qubit quantum-computing emulator executing quantum algorithms at high speed is proposed. By limiting the command of the quantum computing emulator to the minimum function required with the quantum algorithm, probability amplitudes are expressed with one bit and the functions of many qubits are integrated on a field programmable gate array (FPGA). As a result of implementing the emulator in the FPGA, it is found that the emulator has a 250 times higher-speed as compared with a software simulation by a general-purpose processor.
Among the many computational models for quantum computing, the Quantum Circuit Model is the most well-known and used model for interacting with current quantum hardware. The practical implementation of quantum computers is a very active research field. Despite this progress, access to physical quantum computers remains relatively limited. Furthermore, the existing machines are susceptible to random errors due to quantum decoherence, as well as being limited in number of qubits, connectivity and built-in error correction. Simulation on classical hardware is therefore essential to allow quantum algorithm researchers to test and validate new algorithms in a simulated-error environment. Computing systems are becoming increasingly heterogeneous, using a variety of hardware accelerators to speed up computational tasks. One such type of accelerators, Field Programmable Gate Arrays (FPGAs), are reconfigurable circuits that can be programmed using standardized high-level programming models such as OpenCL and SYCL. FPGAs allow to create specialized highly-parallel circuits capable of mimicking the quantum parallelism properties of quantum gates, in particular for the class of quantum algorithms where many different computations can be performed concurrently or as part of a deep pipeline. They also benefit from very high internal memory bandwidth. This paper focuses on the analysis of quantum algorithms for applications in computational fluid dynamics. In this work we introduce novel quantum-circuit implementations of model lattice-based formulations for fluid dynamics, specifically the D1Q3 model using quantum computational basis encoding, as well as, efficient simulation of the circuits using FPGAs. This work forms a step toward quantum circuit formulation of the Lattice Boltzmann Method (LBM). For the quantum circuits implementing the nonlinear equilibrium distribution function in the D1Q3 lattice model, it is shown how circuit transformations can be introduced that facilitate the efficient simulation of the circuits on FPGAs, exploiting their fine-grained parallelism. We show that these transformations allow us to exploit more parallelism on the FPGA and improve memory locality. Preliminary results show that for this class of circuits the introduced transformations improve circuit execution time. We show that FPGA simulation of the reduced circuits results in more than 3× improvement in performance per Watt compared to the CPU simulation. We also present results from evaluating the same kernels on a GPU.
A quantum computing simulation provides the opportunity to explore the behaviors of quantum circuits, study the properties of quantum gates, and develop quantum computing algorithms. Simulating quantum circuits requires geometric time and space complexities, impacting the size of the quantum circuit that can be simulated as well as the respective time required to simulate a particular circuit. Applying the parallelism inherent in the simulation and crafting custom architectures, larger quantum circuits can be simulated. A scalable accelerator architecture is proposed to provide a high performance, highly parallel, accelerator. Among the challenges of creating a scalable architecture is managing parallelism, efficiently routing quantum state components for gate evaluation, and measurement. An example is demonstrated on an Intel Agilex field programmable gate array (FPGA).
Although, there have been considerable advances in quantum technology, a great scale quantum computer will not be available until about a few years. In the meantime, it requires quantum emulators which allow to study the existing quantum algorithms and the design of new ones. We propose a flexible method to emulate quantum circuits which reduces design and processing time. In this context, we propose a design framework that takes advantage of field-programmable gate array (FPGA) parallel processing technology in combination with high-level programming tools provided by Vivado. In order to show the design method working Quantum Fourier Transform (QFT) is implemented. Every step of the design is described and circuit performance is studied for different cases of input vector data sizes.