Currently, the theory of quantum computing is actively developing. Despite the fact that a quantum computer has some features, any algorithm designed for a classical computer can be implemented for a quantum one. The relevance of the topic of quantum computers is confirmed by the fact that even now banking systems, cryptography and encryption of information require enormous resources of computing systems, these are just some examples, but the most important and vivid ones that relate to the everyday life of a huge part of the world's population. A hardware computing core has been developed and simulated, which is the main part of an accelerator based on field-programmable gate array with computer aided design Altera Quartus. Considering the obtained time dependence of the number of cycles required for the impact of a single-qubit quantum gate on a quantum register on the number of qubits and parallel arithmetic logic units in the hardware computing core, when simulating quantum computing, a method was developed to determine the increase in hardware performance and ways to improve the performance of an accelerator based on a hardware computing core were developed. based on field-programmable gate array.
Currently, the theory of quantum computing is actively developing. Despite the fact that a quantum computer has some features, any algorithm designed for a classical computer can be implemented for a quantum one. The relevance of the topic of quantum computers is confirmed by the fact that even now banking systems, cryptography and encryption of information require enormous resources of computing systems, these are just some examples, but the most important and vivid ones that relate to the everyday life of a huge part of the world's population. A hardware computing core has been developed and simulated, which is the main part of an accelerator based on field-programmable gate array with computer aided design Altera Quartus. Considering the obtained time dependence of the number of cycles required for the impact of a single-qubit quantum gate on a quantum register on the number of qubits and parallel arithmetic logic units in the hardware computing core, when simulating quantum computing, a method was developed to determine the increase in hardware performance and ways to improve the performance of an accelerator based on a hardware computing core were developed. based on field-programmable gate array.
The quantum core method is one of the most important methods in quantum machine learning.However, the number of features used for quantum nuclei is limited to a few dozen features.The block product state structure is used as a quantum feature map and the implementation ofprogrammable gate matrices is demonstrated. The relevance of these studies lies in the mathematicaland software modeling and implementation of a quantum computing system as part of thedevelopment of the implementation of a quantum core on FPGA for solving classes of problems ofa classical nature. The scientific novelty of this research area is the development of a hybrid simulatorof the quantum cores of a central processing unit (CPU) and a programmable logic integratedcircuit (FPGA) several orders of magnitude faster than a conventional quantum computingsimulator. This joint development of the implemented quantum core and its efficient FPGA implementation allowed numerical simulation of the quantum core based on gates in terms of inputfeatures, up to 780-dimensional features using 4000 samples. We applied the quantum kernel toimage classification problems using the Fashion-MNIST dataset and showed that the quantumkernel is comparable to Gaussian kernels with optimized throughput. The analysis of the work inthis field has shown that a new qualitative level has now been reached, opening up promising opportunitiesfor the implementation of multi-qubit quantum computing. The prospects for implementationand development are connected not only with technological capabilities, but also with solvingthe issues of building effective quantum systems for solving actual mathematical problems,cryptography problems and control (optimization) problems.
In the past few decades, there has been an acute problem of creating a quantum computer that uses quantum mechanical effects such as quantum parallelism and quantum entanglement for computations. Using these mechanisms, the quantum computer is able to solve some of the NP-class problems in polynomial time. A hardware approach to modeling quantum computing is considered, and a general mathematical model of the operation of a quantum computer is described, and a technique for mathematical modeling of quantum computing is presented. At the stage of consideration of the method of mathematical modeling, the most resource-intensive parts of the model are indicated. Also, issues related to data parallelization on a hardware accelerator, which are planned to be used to simulate quantum computing, were considered, and algorithms for the operation of this type of accelerator were given. A more compact data format is proposed, which is recommended to be used when implementing the accelerator. Using the proposed format, it is possible to reduce the resources spent on elementary arithmetic operations. The possibility of introducing an optimization algorithm to minimize the time spent in computations, as well as to speed up the execution of quantum algorithms in simulators of a quantum computer at the stage of the effect of quantum gates on the quantum register model, is proposed. The results of the optimization algorithm and its comparison with the classical mathematical approach using a software model are presented.
The theory of quantum computing is being actively developed. Despite the fact that quantum computing device has some peculiarities, any task designed for a classical computer can be reproduced on a quantum system. The aim of the research is to develop a methodology for constructing models of quantum systems simulators using hardware simulators. The subject of this research is methods for constructing quantum computing devices and systems. In the course of the research, the system analysis methods and computer modeling, methods of object-oriented design were used. Modern high-level languages were used to solve the problems of constructing a modular quantum system with an open architecture. The work of a quantum microarchitecture using an algorithm for optimizing a quantum computational process has been developed and modeled. A universal methodology for modeling algorithms of a quantum nature using the hardware core and requirements for the mutual operation of software and hardware components for the efficient operation of a quantum system is derived.
A quantum computing simulation provides the opportunity to explore the behaviors of quantum circuits, study the properties of quantum gates, and develop quantum computing algorithms. Simulating quantum circuits requires geometric time and space complexities, impacting the size of the quantum circuit that can be simulated as well as the respective time required to simulate a particular circuit. Applying the parallelism inherent in the simulation and crafting custom architectures, larger quantum circuits can be simulated. A scalable accelerator architecture is proposed to provide a high performance, highly parallel, accelerator. Among the challenges of creating a scalable architecture is managing parallelism, efficiently routing quantum state components for gate evaluation, and measurement. An example is demonstrated on an Intel Agilex field programmable gate array (FPGA).
The speed of a fault-tolerant quantum computer depends in large part on the reaction time of its classical electronics, that is, the total time required by decoders and controllers to determine the outcome of a logical measurement and execute subsequent conditional logical operations. Despite its importance, the reaction time and its impact on the design of a logical microarchitecture of a quantum computer are not well understood. In this work, we perform a detailed system-level analysis of the classical and quantum resource requirements of a surface code based architecture. To this end, we construct a model of the reaction time in which the decoder latency is based on parallel space- and time-window decoding methods. In addition, we draw communication latencies from our envisioned quantum execution environment, which comprises a high-speed network of quantum processing units, controllers, decoders, and high-performance computing nodes. We use this model to estimate the increase in the logical error rate of magic state injections as a function of the reaction time. We then show how the microarchitecture can be optimized with respect to the reaction time, and present full-system quantum resource estimates based on realistic hardware noise parameters for executing utility-scale quantum circuits of the Fermi-Hubbard model (2562 logical qubits and 4×106T gates) and NMR spectral prediction (241 logical qubits and 5.11×1011T gates). We numerically determine the impact of improving reaction time on the code distance required for the core processor and on the size of the resource state factory. Moreover, we analyze how decoder speeds constrain the size of practically executable circuits, and show that state-of-the-art decoders will require a performance improvement of at least an order of magnitude to execute utility-scale quantum algorithms within days.
It is shown that true quantum computers are analog and probabilistic computers and, in fact,they play the role of coprocessors in relation to classical computers. A digital quantum coprocessor consists of digital qubits. Each digital qubit is a finite state machine, the state changes of which is described in the same way as the state changes of an analog qubit. A digital qubit is a chain of digital quantum gates. Each digital quantum gate is digital unit, the state changes of which is described in the same way as the state changes of an analog quantum gate. The main difference between digital qubit and digital quantum gate from analog ones is the presence of memory (more precisely, the possibility of its introduction into their circuit) and its use for organizing calculations. A digital qubit without feedbacks - a digital quantum gate that can be controlled using a classic computer, is a single step of a pipeline with a measurement unit (comparator), a pipeline register and a pipeline trigger at the output. The quantum Fourier transform (QFT) is part of many quantum algorithms, in particular the Shor'sfactorization algorithm. The structures of digital quantum gates, digital qubits, and a digital quantumcoprocessor capable of performing the QFT are presented. The results of the QFT of a multi-qubit digital quantum coprocessor implemented on one FPGA are presented. For this, a IP core generator of multi-qubit quantum coprocessors was created, cores work was simulated. Models were implemented in FPGAs and their time and hardware characteristics were determined. The execution time of one quantum Fourier transform does not depend on the number of qubits in the digital quantum coprocessor and is commensurate with the time of change of the electron spin. The hardware complexity linearly depends on the number of qubits. With an increase in the number of qubits, the rate of true results of QFT decreases, at 64 qubits it is 1.5%, the decrease is nonlinear