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arXiv:2511.10633

Impacts of Decoder Latency on a Utility-Scale Quantum Computer Architecture

Abdullah Khalid, Allyson Silva, Gebremedhin A. Dagnew, Tom Dvir, Oded Wertheim, Motty Gruda, Xiangzhou Kong, Mia Kramer, Zak Webb, Artur Scherer, Masoud Mohseni, Yonatan Cohen, Pooya Ronagh

quant-phSubmitted Nov 13, 2025• Announced Nov 14, 2025• 0 citations• Revised Aug 22, 2026 (v2)
v1 · Nov 13, 2025v2 · Aug 22, 2026
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Abstract

The speed of a fault-tolerant quantum computer depends in large part on the reaction time of its classical electronics, that is, the total time required by decoders and controllers to determine the outcome of a logical measurement and execute subsequent conditional logical operations. Despite its importance, the reaction time and its impact on the design of a logical microarchitecture of a quantum computer are not well understood. In this work, we perform a detailed system-level analysis of the classical and quantum resource requirements of a surface code based architecture. To this end, we construct a model of the reaction time in which the decoder latency is based on parallel space- and time-window decoding methods. In addition, we draw communication latencies from our envisioned quantum execution environment, which comprises a high-speed network of quantum processing units, controllers, decoders, and high-performance computing nodes. We use this model to estimate the increase in the logical error rate of magic state injections as a function of the reaction time. We then show how the microarchitecture can be optimized with respect to the reaction time, and present full-system quantum resource estimates based on realistic hardware noise parameters for executing utility-scale quantum circuits of the Fermi-Hubbard model (2562 logical qubits and $4$$\times$$10^6$ $T$ gates) and NMR spectral prediction (241 logical qubits and $5.11$$\times$$10^{11}$ $T$ gates). We numerically determine the impact of improving reaction time on the code distance required for the core processor and on the size of the resource state factory. Moreover, we analyze how decoder speeds constrain the size of practically executable circuits, and show that state-of-the-art decoders will require a performance improvement of at least an order of magnitude to execute utility-scale quantum algorithms within days.

Comments
27 pages, 10 figures

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Fault-tolerant quantum computing is essential for realizing the substantial computational speedups that quantum computing can bring, but it requires real-time error decoding with high performance. Speculative window decoding improves performance by reducing the time spent waiting for dependencies from prior decoding windows. However, speculative decoders have only been evaluated under the regime of superconducting qubits with fast gate speeds, surface codes, and matching decoders. Since different quantum technologies can have slower gate speeds, we evaluate the performance of speculative decoding under slow gate speeds. We also examine its sensitivity to speculation accuracy, decoder latency, processor count, and workload parallelism, which can vary across different quantum error correction codes, decoders, and hardware platforms. This work presents design principles for identifying when speculative decoding yields the greatest performance improvements. It also reveals the conditions under which non-speculative decoders outperform speculative decoders.
Transitioning quantum computing from laboratory physical demonstrations to practical, utility-scale processing requires bridging a multi-order-of-magnitude gap between physical gate fidelities and algorithmic error thresholds. While fault-tolerant quantum computing relies on quantum error correction to span this divide, traditional evaluation metrics focused on isolated physical components fail to reflect real-world execution capacity. In this Perspective, we analyze the physical and microarchitectural bottlenecks governing scalable quantum compute engines: the spatial footprint trade-offs between code encoding efficiency and hardware routing, the temporal latencies of closed-loop decoding under strict cryogenic thermal budgets, and the structural performance asymmetries of modular multi-chip networks. We argue that overcoming these multi-faceted scalability barriers demands moving beyond single-layer hardware optimizations toward a holistic full-stack co-design paradigm—jointly tailoring error-correcting code topologies, control microarchitectures, and interconnect networks to unlock sustainable logical throughput.