We develop a new model to evaluate the necessary classical computing and networking resources required to support a large-scale fault-tolerant quantum computer based on superconducting qubits and a surface code architecture. We focus specifically on quantum error decoding, which is the main classical computational task required to enable quantum error correction during runtime. Our model reveals that the quantum computer operates at a logical clock speed in the 100-10,000 Hz range, using state-of-the-art quantum error decoders. For a prototypical large-scale quantum chemistry computation, this translates to an overall runtime on the order of months, and this workload is estimated to generate syndrome data for error correction at a rate of 2–500 Gbps depending on whether data compression is used. We estimate the total computational processing power required for online error syndrome decoding equals about 1 petaflop. The results of our analysis show that current computing and networking technology can meet the requirements, in terms of bandwidth, latency, and compute, to support large-scale quantum computation. However, major technological challenges remain both for quantum and classical hardware, including scalable fabrication of high-quality qubits, scalable qubit control, and syndrome communication within a limited power budget.
We develop a new model to evaluate the necessary classical computing and networking resources required to support a large-scale fault-tolerant quantum computer based on superconducting qubits and a surface code architecture. We focus specifically on quantum error decoding, which is the main classical computational task required to enable quantum error correction during runtime. Our model reveals that the quantum computer operates at a logical clock speed in the 100-10,000 Hz range, using state-of-the-art quantum error decoders. For a prototypical large-scale quantum chemistry computation, this translates to an overall runtime on the order of months, and this workload is estimated to generate syndrome data for error correction at a rate of 2–500 Gbps depending on whether data compression is used. We estimate the total computational processing power required for online error syndrome decoding equals about 1 petaflop. The results of our analysis show that current computing and networking technology can meet the requirements, in terms of bandwidth, latency, and compute, to support large-scale quantum computation. However, major technological challenges remain both for quantum and classical hardware, including scalable fabrication of high-quality qubits, scalable qubit control, and syndrome communication within a limited power budget.
The speed of a fault-tolerant quantum computer depends in large part on the reaction time of its classical electronics, that is, the total time required by decoders and controllers to determine the outcome of a logical measurement and execute subsequent conditional logical operations. Despite its importance, the reaction time and its impact on the design of a logical microarchitecture of a quantum computer are not well understood. In this work, we perform a detailed system-level analysis of the classical and quantum resource requirements of a surface code based architecture. To this end, we construct a model of the reaction time in which the decoder latency is based on parallel space- and time-window decoding methods. In addition, we draw communication latencies from our envisioned quantum execution environment, which comprises a high-speed network of quantum processing units, controllers, decoders, and high-performance computing nodes. We use this model to estimate the increase in the logical error rate of magic state injections as a function of the reaction time. We then show how the microarchitecture can be optimized with respect to the reaction time, and present full-system quantum resource estimates based on realistic hardware noise parameters for executing utility-scale quantum circuits of the Fermi-Hubbard model (2562 logical qubits and 4×106T gates) and NMR spectral prediction (241 logical qubits and 5.11×1011T gates). We numerically determine the impact of improving reaction time on the code distance required for the core processor and on the size of the resource state factory. Moreover, we analyze how decoder speeds constrain the size of practically executable circuits, and show that state-of-the-art decoders will require a performance improvement of at least an order of magnitude to execute utility-scale quantum algorithms within days.
Quantum computing may solve selected classes of problems more efficiently than classical computers, with applications in areas such as cryptography, chemistry, and optimization. However, current quantum systems remain limited in scale and reliability and depend on substantial classical-computing support. This thesis investigates this challenge in two complementary contexts: classical simulation, where efficient computation enables the exploration of larger quantum systems; and quantum error correction, where efficient real-time decoding enables more reliable quantum operation.The first part examines the classical simulation of quantum computers, focusing on the computational and memory challenges that limit its scalability. It organizes the field across device, gate, and algorithmic levels, with particular attention to state-vector, path-based, hybrid, and tensor-based methods. The survey relates their computation, memory, data-movement, and communication bottlenecks to acceleration approaches for CPUs, GPUs, FPGAs, and distributed systems. It further highlights recurring optimization strategies, including reduced precision, data compression, parallel execution, improved memory locality, specialized matrix units, and reconfigurable hardware, providing a common framework for current techniques and future acceleration opportunities.The second part addresses the real-time classical processing required for quantum error correction. Starting from a high-accuracy Graph Neural Network surface-code decoder, it applies algorithm-hardware co-design through hardware-guided pruning and retraining, input-graph filtering, quantization, and a custom FPGA architecture. For code distances up to d=7, the resulting designs satisfy both max-latency and average-latency decoding requirements while reducing the logical error rate by 13% and 40%, respectively, compared with the evaluated Minimum Weight Perfect Matching baseline.Together, these works show how classical computer-architecture techniques can support quantum computing from scalable exploration through simulation to reliable operation through real-time error correction.
Quantum error correction (QEC) is indispensable for building scalable fault-tolerant quantum computers. Effective QEC demands stringent real-time decoding: the decoder must process syndrome measurements and determine corrections within a time scale--typically on the order of microseconds, to avoid data backlog. Scaling to large number of logical qubits further necessitates significant computational resources. In this work, we propose an architecture, called \emph{THQLink}, for real-time decoding of quantum error correction codes using high-performance computing (HPC) resources. The network connecting the HPC and the control system of quantum processing unit (QPU) is built on TH-Express and can be adapted to different quantum technologies and their associated control stacks. We report a round-trip latency of 2.944 μs on average, with an incremental overhead of 130 ns per additional hop. Using a parallel window strategy, we demonstrate real-time decoding (1 μs per QEC round) of the surface code up to distance 19 using a matching-based decoder on CPUs. Our work presents a scalable framework for real-time decoding in fault-tolerant quantum computing. It can be readily applied to quantum-centric supercomputers that feature tight integration between QPU and HPC resources, thereby enabling efficient support for hybrid quantum-classical algorithms and computation-intensive workloads offloaded from the QPU.
The promise of fault-tolerant quantum computation rests on its ability to solve certain intractable problems exponentially faster than classical computers. However, this theoretical promise is challenged by a cascade of interconnected physical bottlenecks, where the act of scaling quantum resources to suppress errors creates insurmountable thermal and classical processing loads. This paper develops an integrated thermal equilibrium model that quantitatively links physical gate fidelity, quantum error correction (QEC) overhead, and cryogenic cooling capacity to determine the viability of a large-scale system. Through numerical analysis of a system designed to execute Shor’s algorithm, the model demonstrates that even under optimistic technological assumptions, the required physical resources—in terms of qubit count, cooling power, and classical decoding speed—remain orders of magnitude beyond plausible near-term capabilities. The findings indicate that the primary barrier to scalable quantum computation is not a single engineering challenge but a systemic, multi-physics resource gap, where the polynomial scaling of classical support systems fails to keep pace with the exponential demands of the quantum core. This suggests that progress requires a holistic co-design of algorithms, hardware, and control systems rather than isolated improvements in qubit count alone.
Quantum computing has the potential to transform information technology by offering algorithms for certain tasks, such as quantum simulation, that are vastly more efficient than what is possible with any classical device. But experimentally implementing practical quantum information processing is a very difficult task. Here we study two important, and closely related, aspects of this challenge: architectures for quantum computing, and quantum error correction Exquisite quantum control has now been achieved in small ion traps, in nitrogen-vacancy centres and in superconducting qubit clusters, but the challenge remains of how to scale these systems to build practical quantum devices. In Part I of this thesis we analyse one approach to building a scalable quantum computer by networking together many simple processor cells, thus avoiding the need to create a single complex structure. The difficulty is that realistic quantum links are very error prone. Here we describe a method by which even these error-prone cells can perform quantum error correction. Groups of cells generate and purify shared resource states, which then enable stabilization of topologically encoded data. Given a realistically noisy network (10% error rate) we find that our protocol can succeed provided that all intra-cell error rates are below 0.8%. Furthermore, we show that with some adjustments, the protocols we employ can be made robust also against high levels of loss in the network interconnects. We go on to analyse the potential running speed of such a device. Using levels of fidelity that are either already achievable in experimental systems, or will be in the near-future, we find that employing a surface code approach in a highly noisy and lossy network architecture can result in kilohertz computer clock speeds. In Part II we consider the question of quantum error correction beyond the surface code. We consider several families of topological codes, and determine the minimum requirements to demonstrate proof-of-principle error suppression in each type of code. A particularly promising code is the gauge color code, which admits a universal transversal gate set. Furthermore, a recent result of Bombin shows the gauge color code supports an error-correction protocol that achieves tolerance to noisy measurements without the need for repeated measurements, so called single-shot error correction. Here, we demonstrate the promise of single-shot error correction by designing a decoder and investigating its performance. We simulate fault-tolerant error correction with the gauge color code, and estimate a sustainable error rate, i.e. the threshold for the long time limit, of ~0.31% for a phenomenological noise model using a simple decoding algorithm.
Quantum computation promises significant computational advantages over classical computation for some problems. However, quantum hardware suffers from much higher error rates than in classical hardware. As a result, extensive quantum error correction is required to execute a useful quantum algorithm. The decoder is a key component of the error correction scheme whose role is to identify errors faster than they accumulate in the quantum computer and that must be implemented with minimum hardware resources in order to scale to the regime of practical applications. In this work, we consider surface code error correction, which is the most popular family of error correcting codes for quantum computing, and we design a decoder micro-architecture for the Union-Find decoding algorithm. We propose a three-stage fully pipelined hardware implementation of the decoder that significantly speeds up the decoder. Then, we optimize the amount of decoding hardware required to perform error correction simultaneously over all the logical qubits of the quantum computer. By sharing resources between logical qubits, we obtain a 67% reduction of the number of hardware units and the memory capacity is reduced by 70%. Moreover, we reduce the bandwidth required for the decoding process by a factor at least 30x using low-overhead compression algorithms. Finally, we provide numerical evidence that our optimized micro-architecture can be executed fast enough to correct errors in a quantum computer.