Logic Design of a Single-Flux-Quantum (SFQ) 2x2 Unit Switch for Banyan Networks

Y Kameda, Shinichi Yorozu, M. Hidaka +1 more

Hirotaka Terai, 義男 亀田, Shinichi Yorozu +1 more

A Tandem-Banyan network switch (TBNS) based on superconductor single-flux-quantum technologies is described. Its switching core consists of multiple Banyan networks and transmission checkers (TMCs) connected sequentially. Numerical simulation demonstrated that the maximum throughput of TBNS is much higher than that of the input-buffer-type Batcher-Banyan network switch, while the amount of hardware is comparable with that of a Batcher-Banyan network switch. The two-bit code extraction part of the address decoder of the TMC circuit was designed and implemented using the SFQ cell library developed for NEC Nb standard fabrication process. The correct logic operation was experimentally observed with a bias margin of around ±10%. This switch is suitable for managing the huge amount of data traffic that will be carried in future backbone networks.

Y. Kameda, Shinichi Yorozu, Shuichi Tahara

We are developing a single-flux-quantum (SFQ) packet switch for over 1-Tb/s switching systems. Investigation of several switch topologies leads us to select the Batcher-Banyan packet switch because of its simplicity and regularity. The packet switch structure we propose consists of simple 2/spl times/2 unit switches each connected by speeded-up internal links. Numeric simulation showed that the speeded-up links greatly improved the throughput by resolving packet blocking, which is a major drawback of the Banyan switch. High throughput compatible to a crossbar switch was attained by using links whose speed was quadrupled. Moreover, the throughput did not decrease even though the number of input/output ports increased. Taking the speed of SFQ basic gates into account, the cycle time of the 2/spl times/2 unit switch reaches 25 ps, which is sufficient to achieve the 40-GHz operation. If unit switches are connected by quadrupled internal links, the Batcher-Banyan switch can accept the 10-Gb/s external input rate per channel. This indicates that the total throughput of a 128/spl times/128 switch exceeds 1 Tb/s. The unit switch was designed down to the SFQ gate level. To design a large SFQ circuit, we built several "standard" SFQ cells whose shape was square or rectangular with a unit width and height. Such shapes make it easier to place and connect a number of cells. We show some experimental results of testing SFQ standard cells and logic circuits.

Koki Ishida, Tomonori Tsuhata, Tanaka Masamitsu +2 more

Nakagawa Takahiro, Yoshihito Hashimoto, 義男 亀田 +3 more

Shinichi Yorozu, Y. Kameda, Y. Hashimoto +1 more

Large-scale telecommunication systems in the larger nationwide network of the next decade will require routers having a packet switching throughput capacity of over several-tens Tbps. In such future high-end routers, the packet switch, which is the biggest bottleneck of the router, will need higher processing speeds than semiconductor devices. In this paper, we describe an SFQ packet switch architecture that is used in the internal speed-up Banyan network. According to the architecture we have designed and demonstrated a deep-pipelined 2/spl times/2 packet switch logic circuit, which is the key element in a packet switch, by applying two technological advances regarding design methodology and packaging. This circuit is among the largest SFQ random logic circuits yet reported.