Challenges
Datasets
Workspaces
Papers
Discussions
Leaderboard
Log inSign up
Challenges
Datasets
Workspaces
Papers
Discussions
Leaderboard
Blog
Job Board
Q3AS

© 2026 Aqora Quantum S.A.S.

TermsPrivacyLegal Notice

IEICE Technical Report; IEICE Tech. Rep.

Logic Design of A Single-Flux-Quantum Microprocessor

Koki Ishida, Tomonori Tsuhata, Tanaka Masamitsu, Takatsugu Ono, Koji Inoue

Published Nov 24, 2015• 0 citations
OpenAlex

Related papers

Design of a Tiny Microprocessor Based on the Single-Flux-Quantum Circuit Technology

Nobuyuki Yoshikawa, Fumiya Matsuzaki, Nobuo Nakajima +3 more

International Conference on Solid State Devices and Materials (SSDM)•Sep 18, 2002•0 citations

Design and evaluation of data-path for low-power single-flux-quantum microprocessors

Yuhi Hayakawa, Takata Kensuke, Tanaka Masamitsu +1 more

IEICE Technical Report; IEICE Tech. Rep.•Jul 15, 2013•0 citations

Design of a datapath for single-flux-quantum microprocessors with multiple ALUs

Masamitsu Tanaka, Takaharu Kondo, Tadashi Kawamoto +8 more

Physica C Superconductivity•Jul 26, 2005•6 citations

A new design approach for control circuits of pipelined single-flux-quantum microprocessors

Yuki Yamanashi, A Akimoto, Nobuyuki Yoshikawa +6 more

A novel method of design for controllers of pipelined microprocessors using single-flux-quantum (SFQ) logic has been proposed. The proposed design approach is based on one hot encoding and is very suitable for designing a finite state machine using SFQ logic circuits, where each internal state of the microprocessor is represented by a flip-flop. In this approach, decoding of the internal state can be performed instantaneously, in contrast to the case in the conventional method using a binary state register. Moreover, pipelining is effectively implemented without increasing the circuit size because no pipeline registers are required in the one hot encoding. By using this method, we have designed a controller for our new SFQ microprocessors, which employs pipelining. The number of Josephson junctions of the newly designed controller is 1067, while the previous version without pipelining contains 1721 Josephson junctions. These results indicate that the proposed design approach is very effective for pipelined SFQ microprocessors. We have implemented a new controller using the NEC 2.5 kA cm −2 Nb standard process and confirmed its correct operation experimentally.

Superconductor Science and Technology•Mar 16, 2006•5 citations

Low-Voltage Bit-Serial Single-Flux-Quantum Microprocessor for Integrating Memories

Ryo Sato, Takata Kensuke, Masamitsu Tanaka +3 more

We report an energy-efficient bit-serial microprocessor based on single-flux-quantum (SFQ) logic, called CORE e3, using a low-voltage bias technique. This microprocessor was designed for integrating memories, and we developed it to investigate the efficient use of hardware and energy, using the low-voltage rapid single-flux-quantum (LV-RSFQ) technique. We implemented the CORE e3 and its test circuit using a 10-kA/cm2Nb process. We confirmed via logic simulations that all instructions were executed correctly with a 1-GHz system clock. We expect a 3.51 fold improvement in energy efficiency.

IEEE International Superconductive Electronics Conference (ISEC)•Jul 1, 2015•2 citations

A single-flux-quantum logic prototype microprocessor

Masamitsu Tanaka, Fumiya Matsuzaki, Takaharu Kondo +7 more

The complete operation of a microprocessor prototype based on the single-flux-quantum (SFQ) logic is described. The 8b SFQ microprocessor, fabricated using niobium Josephson-junction technology, performs computation at a 15.2GHz clock rate with power consumption of 1.6mW. The /spl mu/P contains 5000 Josephson junctions and 1300 cells on a 5mm/sup 2/ IC.

Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference•Sep 28, 2004•59 citations
A novel method of design for controllers of pipelined microprocessors using single-flux-quantum (SFQ) logic has been proposed. The proposed design approach is based on one hot encoding and is very suitable for designing a finite state machine using SFQ logic circuits, where each internal state of the microprocessor is represented by a flip-flop. In this approach, decoding of the internal state can be performed instantaneously, in contrast to the case in the conventional method using a binary state register. Moreover, pipelining is effectively implemented without increasing the circuit size because no pipeline registers are required in the one hot encoding. By using this method, we have designed a controller for our new SFQ microprocessors, which employs pipelining. The number of Josephson junctions of the newly designed controller is 1067, while the previous version without pipelining contains 1721 Josephson junctions. These results indicate that the proposed design approach is very effective for pipelined SFQ microprocessors. We have implemented a new controller using the NEC 2.5 kA cm −2 Nb standard process and confirmed its correct operation experimentally.
We report an energy-efficient bit-serial microprocessor based on single-flux-quantum (SFQ) logic, called CORE e3, using a low-voltage bias technique. This microprocessor was designed for integrating memories, and we developed it to investigate the efficient use of hardware and energy, using the low-voltage rapid single-flux-quantum (LV-RSFQ) technique. We implemented the CORE e3 and its test circuit using a 10-kA/cm2Nb process. We confirmed via logic simulations that all instructions were executed correctly with a 1-GHz system clock. We expect a 3.51 fold improvement in energy efficiency.