Single Flux Quantum Integrated Circuit Design

Gleb Krylov, Tahereh Jabbari, Eby G. Friedman

Yoshiki Arita, Nobuyuki Yoshikawa, Baba Toshihiko

Single flux quantum (SFQ) circuits and optical circuits are expected to be used in next-generation integrated circuits. This study investigates basic technologies for integrating optical circuits with SFQ circuits to exploit the advantages of both technologies. We calculated, designed and evaluated metal-clad waveguides, which can be fabricated by the ISTEC standard process (STD2). Light propagates along an 830-μm-long waveguide with a propagation loss of 16 dB/mm. We also designed and evaluated an optical-electrical (O-E) converter that uses a Josephson junction, which can be fabricated by the same process used to fabricate the SFQ circuits. When an optical signal with a peak power of 1.15 mW at 1.548 μm is input, the Josephson O-E converter generates SFQ pulses.

Kiyotaka Nakajima

Hannes Töpfer, Thomas Ortlepp

The article describes the activities aimed at bringing superconductive high-speed electronics towards maturity.Integrated circuits based on the effects in superconducting materials have become feasible for some years already.The main focus lies on the so-called Rapid Single-Flux-Quantum (RSFQ) electronics which allows the combination of high operation frequencies (well above 20 GHz) with very low energy consumption when logical states are changed.Thus, this circuit technology exhibits a promising potential for realising energy-efficient modules for signal processing and computing.Recently, a dedicated design infrastructure has been developed in Europe.Closely associated is a foundry for digital RSFQ integrated circuits so that the fabrication of integrated circuits is viable.In the contribution, the basic features of the RSFQ circuit design are addressed with special emphasis on implementation on the wafer scale.

Y. Tukel, Ali Bozbey, C.A. Tunc

Successful fabrication and demonstration of complex Rapid Single Flux Quantum (RSFQ) circuits depend heavily on the reliability of the cell library that is used for the design. In large-scale RSFQ integrated circuits, delay fluctuations (jitter) of each cell may occur due to fabrication tolerances. The fabrication-induced jitter of each cell might accumulate at each stage and bring out larger variations comparable with the designed delay. If such jitter is not considered while arranging timing of the circuit, it may cause the circuit to malfunction due to the shifting of SFQ pulses. Therefore, it is important to optimize and determine the delay fluctuations of each cell well before designing a large-scale integrated circuit. There are quite a number of parameters that affect the functioning and the performance of a logic gate; hence, an optimization tool is required. In this study, the progress on development of an optimization tool for a digital RSFQ cell library composed of fundamental logic gates, such as Josephson transmission lines, D-flip-flops, T-Flip-flops, splitters, and mergers are presented. Particle swarm optimization is used for an optimization algorithm, which determines the circuit parameters with minimum delay and/or jitter satisfying the required critical margin conditions.

Kiyotaka Nakajima