The Quantum Approximate Optimisation Algorithm is the canonical near-term heuristic, yet on real superconducting hardware its behaviour is set by device physics, not by the algorithm. Hardware demonstrations rarely prove the intended coupling is realised, that genuine entanglement is prepared, or what controls it. We report a pre-registered single-device study on the nine-qubit superconducting processor Red at the Barcelona Supercomputing Center, using its five-qubit component. Across six calibrations we certify bipartite entanglement of a corrected QAOA cost layer on the good coupler at depth one by two-qubit tomographic negativity: 0.077, BCa 95% CI [0.065, 0.091], excluding zero every day, while the coupling-off twin stays separable and the degraded coupler equals zero. We then measure the device physics directly: in a pre-registered manipulation on a fixed Bell preparation (not the QAOA layer), reducing the CZ pulse amplitude causally reduces the certified negativity along a positive, well-fit slope (R^2 = 0.83-0.96), every rung-level interval excluding zero and surviving Holm and Benjamini-Hochberg correction. This is a local linearisation of a peaked response, not a global monotone law: the negativity peaks at conditional phase |zeta| = pi, which the nominal amplitude overshoots. The J=0 twin is a separate off-state control and the fringe visibility is constant, so the effect is coherent. The average gate fidelity is non-monotone in the drive and is reported only as a diagnostic. A per-circuit statevector guardrail excludes a diagonal compilation fault we disclose and repair. A randomized-measurement witness is consistent with entanglement but underpowered. The certificate collapses by depth three, and a pre-registered sixteen-instance depth-three ensemble shows no optimisation signal (one-sided Wilcoxon p = 0.15). We claim no advantage; the instances are classically trivial.
The Quantum Approximate Optimisation Algorithm is the canonical near-term heuristic, yet on real superconducting hardware its behaviour is set by device physics, not by the algorithm. Hardware demonstrations rarely prove the intended coupling is realised, that genuine entanglement is prepared, or what controls it. We report a pre-registered single-device study on the nine-qubit superconducting processor Red at the Barcelona Supercomputing Center, using its five-qubit component. Across six calibrations we certify bipartite entanglement of a corrected QAOA cost layer on the good coupler at depth one by two-qubit tomographic negativity: 0.077, BCa 95% CI [0.065, 0.091], excluding zero every day, while the coupling-off twin stays separable and the degraded coupler equals zero. We then measure the device physics directly: in a pre-registered manipulation on a fixed Bell preparation (not the QAOA layer), reducing the CZ pulse amplitude causally reduces the certified negativity along a positive, well-fit slope (R^2 = 0.83-0.96), every rung-level interval excluding zero and surviving Holm and Benjamini-Hochberg correction. This is a local linearisation of a peaked response, not a global monotone law: the negativity peaks at conditional phase |zeta| = pi, which the nominal amplitude overshoots. The J=0 twin is a separate off-state control and the fringe visibility is constant, so the effect is coherent. The average gate fidelity is non-monotone in the drive and is reported only as a diagnostic. A per-circuit statevector guardrail excludes a diagonal compilation fault we disclose and repair. A randomized-measurement witness is consistent with entanglement but underpowered. The certificate collapses by depth three, and a pre-registered sixteen-instance depth-three ensemble shows no optimisation signal (one-sided Wilcoxon p = 0.15). We claim no advantage; the instances are classically trivial.
Greenberger-Horne-Zeilinger (GHZ) states are a widely used benchmark for studying multipartite entanglement and coherence in quantum processors. In this work, GHZ states of increasing size were prepared on the 156-qubit IBM Quantum processor ibm_marrakesh and certified using a fidelity-based entanglement witness. State coherence was extracted from parity-oscillation measurements using the multiple-quantum-coherence method. The study investigates how a combination of practical error-reduction techniques affects the largest GHZ state that can be certified on open-access superconducting hardware. These techniques include depth-minimized entangling trees, calibration-aware qubit selection, dynamical decoupling with gate and measurement twirling, and matrix-free readout-error mitigation. A naive implementation fails at larger system sizes, while depth-optimized preparation certifies entanglement up to 14 qubits. Calibration-aware qubit selection extends this to 16 qubits, and readout-error mitigation enables certification of genuine multipartite entanglement up to 18 qubits with a measured fidelity exceeding the witness threshold. The results show that the achievable certification size is determined primarily by the quality of the selected qubit region rather than by the total number of qubits available on the processor. The observed non-monotonic dependence of fidelity on system size reflects variations in local device performance. These findings illustrate the impact of hardware-aware compilation and error-mitigation strategies on entanglement certification using publicly accessible quantum computing platforms.
Limited qubit connectivity is a central architectural constraint in superconducting quantum processors, whose planar layouts require additional gates to mediate interactions between distant qubits. Here, we use the AshN control scheme, where rich two-qubit control on every nearest-neighbour pair allows a logical interaction and the required qubit routing to be merged into a single native operation, effectively transforming a sparse hardware graph into a more connected computational architecture. For the benchmark instances studied, the resulting synthesis capability enables reliable execution on constrained one- and two-dimensional lattices, with compiled two-qubit gate counts approaching those of an all-to-all-connected reference. Across seven benchmark circuits on one- and two-dimensional topologies, the AshN-based implementation achieves geometric-mean reductions of 45.2% and 43.7% in two-qubit gate count compared with controlled-Z-based compilation, respectively. Using AshN gates, we prepare an eight-qubit two-excitation Dicke state with a fidelity of 0.736 and certify its genuine multipartite entanglement using a fully positive-partial-transpose witness, whereas the same witness does not certify entanglement for the CZ-based implementation. The state fidelity and entanglement certification remain robust across the tested lattice configurations, including those with up to three connectivity defects. Our work establishes native-gate engineering as a practical approach to mitigating connectivity constraints.
Quantum error correction imposes stringent requirements on the underlying hardware: all core operations of a quantum processor – single-qubit gates, two-qubit entangling gates, qubit readout, and qubit reset – must operate well below the error thresholds of leading codes. While such thresholds have already been crossed in several platforms, the associated overhead in physical qubits and circuit depth remains extremely sensitive to the physical error rate. This thesis investigates how far a superconducting platform based on transmon qubits can be pushed toward its physical limits, and how architectural and control choices can be optimized to reduce the overhead required for fault-tolerant quantum computation. First, we develop and characterize tunable-coupler architectures that enable fast, high-fidelity controlled-Z (CZ) gates. A long-distance coupler increases the qubit-qubit separation, freeing chip area for additional on-chip components, while still achieving CZ fidelities above 99.8%. Building on this, we optimize the qubit-coupler coupling to simultaneously support high-performance single- and two-qubit gates. We achieve simultaneous single- and two-qubit gate fidelities exceeding 99.9% on the same chip using a CZ calibration experiment based on our phase-averaged leakage error amplification (PALEA) protocol. PALEA coherently amplifies small over- and under-rotations of the diabatic CZ gate, making calibration errors easier to detect and correct. Second, we address single-qubit gates. Using spectrally engineered FAST-DRAG and higherderivative DRAG pulses, we demonstrate sub-8 ns gates with errors of order 10!" and strongly suppressed leakage. Third, we address readout by combining shelving to a higher qubit level with Purcell-filtered resonators and quantum-limited amplification, achieving readout errors below 10!#. Beyond the transmon workhorse, we explore the unimon qubit, which combines large anharmonicity with reduced charge sensitivity, and investigate a quantum circuit refrigerator as an integrated resource for fast, unconditional qubit reset via engineered dissipation. Finally, we demonstrate a cryogenic microwave link between two dilution refrigerators, enabling remote state transfer and entanglement over a five-meter distance and illustrating a path toward modular and distributed superconducting quantum processors. Together, these results show that with careful co-design of device layout, coupling topology, pulse shaping, and calibration protocols, all core operations – except qubit reset – of a superconducting quantum processor can be operated in the 10!#–10!" error regime within a coherent hardware and control stack, substantially lowering the resource overhead required for future fault-tolerant architectures.
Achieving high-fidelity single-qubit gates, two-qubit gates, and qubit readout is critical for building scalable, error-corrected quantum computers. However, device parameters that enhance one operation often degrade the others, making simultaneous optimization challenging. Here, we demonstrate that careful tuning of qubit-coupler coupling strengths in a superconducting circuit with two transmon qubits coupled via a tunable coupler enables high-fidelity single- and two-qubit gates, without compromising readout performance. Furthermore, we introduce a new calibration protocol for diabatic controlled- Z gates, phased-averaged leakage error amplification (PALEA), which enables efficient suppression of coherent gate errors and leakage to noncomputational states. Using PALEA in combination with careful tuning of qubit-coupler coupling strengths, we achieve a 40 h-averaged CZ gate fidelity of 99.93 %, simultaneous single-qubit gate fidelities of 99.98 %, and readout fidelities over 99.94 % in a single device. Our results demonstrate a viable path toward scaling up superconducting quantum processors while maintaining consistently high gate and readout fidelities.
Preprint; not peer reviewed. We report a hardware-oriented quantum sampling experiment motivated by Hidden Code Sampling (HCS), while explicitly not claiming an end-to-end implementation of the original HCS PeakVerification–SyndromeVerification protocol. A full-width 60-qubit circuit derived from a sparse trivariate-bicycle CSS construction was embedded without swaps on a 108-qubit superconducting processor and compiled to native RX, RZ, and controlled-Z operations. The base circuit contains 180 logical two-qubit rotations and 360 native controlled-Z gates. Local unitary folding produced stress instances with factors 1, 3, and 5, containing respectively 360, 1080, and 1800 controlled-Z gates. A pilot run was used only to identify and freeze an endian-corrected two-feature local parity witness. The confirmatory dataset consists of three completed QPU executions at folding factors 1, 3, and 5. The final analysis includes only execution records whose frozen QASM identities and authorization hashes match the preregistered confirmatory panel. Each science circuit received 10,000 shots, and each of four calibration patterns received 4,000 shots in both the pre- and post-experiment calibration periods. Simultaneous finite-shot lower confidence bounds combine Clopper–Pearson calibration intervals, a pre/post drift hull, inverse assignment-channel correction, an empirical Bernstein bound, and worst-case optimization over the calibration box. The certified margins are 0.2953, 0.2858, and 0.3148 at folding factors 1, 3, and 5, respectively. All three folds pass, and the maximum calibration-parameter drift is 0.0065. Within a preregistered classical attack suite, the conditional operation-count gap is γ = 6.555, above the registered target of 6.0. This result is an operation-count certificate relative to the registered classical attacks. It is not a wall-clock quantum advantage claim, not a full-distribution total-variation certificate, and not an experimental implementation of the exact HCS protocol. Quantum circuits were submitted to the Rigetti Cepheus-1-108Q superconducting processor through the Open Quantum platform, operated by Quantum Rings, using the Open Quantum Python SDK. This acknowledgment does not imply endorsement by Quantum Rings of the findings, interpretations, or conclusions reported in this work. The deposited files include the preprint, LaTeX sources, sanitized confirmatory QASM files, aggregate certificate metrics, integrity manifests, and publication-compliance documentation. Authentication credentials, account metadata, organization identifiers, provider job identifiers, private provider records, and the private audit archive are excluded.
The quantum approximate optimization algorithm (QAOA) is a promising quantum-classical hybrid technique to solve combinatorial optimization problems in near-term gate-based noisy quantum devices. In QAOA, the objective is a function of the quantum state, which itself is a function of the gate parameters of a multi-level parameterized quantum circuit (PQC). A classical optimizer varies the continuous gate parameters to generate distributions (quantum state) with significant support to the optimal solution. Even at the lowest circuit depth, QAOA offers non-trivial provable performance guarantee which is expected to increase with the circuit depth. However, the existing analysis fails to consider non-idealities in the qubit quality i.e., short lifetime and imperfect gate operations in realistic quantum hardware. In this article, we investigate the impact of various noise sources on the performance of QAOA both in simulation and on a real quantum computer from IBM. Our analyses indicate that the optimal number of stages (p-value) for any QAOA instance is limited by the noise characteristics (gate error, coherence time, etc.) of the target hardware as opposed to the current perception that higher-depth QAOA will provide monotonically better performance for a given problem compared to the low-depth implementations.