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Hardware-Oriented Hidden-Code-Sampling-Inspired Certification on a 60-Qubit Superconducting Processor

Abdelmalik Berrada

Published Jul 31, 2026• 0 citations
Publisher

Abstract

Preprint; not peer reviewed. We report a hardware-oriented quantum sampling experiment motivated by Hidden Code Sampling (HCS), while explicitly not claiming an end-to-end implementation of the original HCS PeakVerification–SyndromeVerification protocol. A full-width 60-qubit circuit derived from a sparse trivariate-bicycle CSS construction was embedded without swaps on a 108-qubit superconducting processor and compiled to native RX, RZ, and controlled-Z operations. The base circuit contains 180 logical two-qubit rotations and 360 native controlled-Z gates. Local unitary folding produced stress instances with factors 1, 3, and 5, containing respectively 360, 1080, and 1800 controlled-Z gates. A pilot run was used only to identify and freeze an endian-corrected two-feature local parity witness. The confirmatory dataset consists of three completed QPU executions at folding factors 1, 3, and 5. The final analysis includes only execution records whose frozen QASM identities and authorization hashes match the preregistered confirmatory panel. Each science circuit received 10,000 shots, and each of four calibration patterns received 4,000 shots in both the pre- and post-experiment calibration periods. Simultaneous finite-shot lower confidence bounds combine Clopper–Pearson calibration intervals, a pre/post drift hull, inverse assignment-channel correction, an empirical Bernstein bound, and worst-case optimization over the calibration box. The certified margins are 0.2953, 0.2858, and 0.3148 at folding factors 1, 3, and 5, respectively. All three folds pass, and the maximum calibration-parameter drift is 0.0065. Within a preregistered classical attack suite, the conditional operation-count gap is γ = 6.555, above the registered target of 6.0. This result is an operation-count certificate relative to the registered classical attacks. It is not a wall-clock quantum advantage claim, not a full-distribution total-variation certificate, and not an experimental implementation of the exact HCS protocol. Quantum circuits were submitted to the Rigetti Cepheus-1-108Q superconducting processor through the Open Quantum platform, operated by Quantum Rings, using the Open Quantum Python SDK. This acknowledgment does not imply endorsement by Quantum Rings of the findings, interpretations, or conclusions reported in this work. The deposited files include the preprint, LaTeX sources, sanitized confirmatory QASM files, aggregate certificate metrics, integrity manifests, and publication-compliance documentation. Authentication credentials, account metadata, organization identifiers, provider job identifiers, private provider records, and the private audit archive are excluded.

DOI
10.5281/zenodo.21724981

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Preprint; not peer reviewed. We report a hardware-oriented quantum sampling experiment motivated by Hidden Code Sampling (HCS), while explicitly not claiming an end-to-end implementation of the original HCS PeakVerification–SyndromeVerification protocol. A full-width 60-qubit circuit derived from a sparse trivariate-bicycle CSS construction was embedded without swaps on a 108-qubit superconducting processor and compiled to native RX, RZ, and controlled-Z operations. The base circuit contains 180 logical two-qubit rotations and 360 native controlled-Z gates. Local unitary folding produced stress instances with factors 1, 3, and 5, containing respectively 360, 1080, and 1800 controlled-Z gates. A pilot run was used only to identify and freeze an endian-corrected two-feature local parity witness. The confirmatory dataset consists of three completed QPU executions at folding factors 1, 3, and 5. The final analysis includes only execution records whose frozen QASM identities and authorization hashes match the preregistered confirmatory panel. Each science circuit received 10,000 shots, and each of four calibration patterns received 4,000 shots in both the pre- and post-experiment calibration periods. Simultaneous finite-shot lower confidence bounds combine Clopper–Pearson calibration intervals, a pre/post drift hull, inverse assignment-channel correction, an empirical Bernstein bound, and worst-case optimization over the calibration box. The certified margins are 0.2953, 0.2858, and 0.3148 at folding factors 1, 3, and 5, respectively. All three folds pass, and the maximum calibration-parameter drift is 0.0065. Within a preregistered classical attack suite, the conditional operation-count gap is γ = 6.555, above the registered target of 6.0. This result is an operation-count certificate relative to the registered classical attacks. It is not a wall-clock quantum advantage claim, not a full-distribution total-variation certificate, and not an experimental implementation of the exact HCS protocol. Quantum circuits were submitted to the Rigetti Cepheus-1-108Q superconducting processor through the Open Quantum platform, operated by Quantum Rings, using the Open Quantum Python SDK. This acknowledgment does not imply endorsement by Quantum Rings of the findings, interpretations, or conclusions reported in this work. The deposited files include the preprint, LaTeX sources, sanitized confirmatory QASM files, aggregate certificate metrics, integrity manifests, and publication-compliance documentation. Authentication credentials, account metadata, organization identifiers, provider job identifiers, private provider records, and the private audit archive are excluded.
SSAF's central falsifiable prediction, NS1, requires that under a witness-confirmed fixed classical context, the reduced dynamics of a probe carry no dependence on the quantum state: all fitted rate parameters are functions of the context alone. This record reports a preregistered pilot execution of the NS1 protocol on the superconducting processor ibm_fez, using target qubit 6 and independent witness qubit 10. The independent context witness passed its two-part gate. Raw stability gave p = 0.3617, and witness-rate homogeneity gave p = 0.9998. The primary endpoint found that one shared affine reduced-evolution law accounted for an informationally complete set of eight target preparations, with a leave-one-out statistic of 176.21 against a parametric-bootstrap null 95% quantile of 253.40 and a cross-validation p-value of 0.6167. The secondary endpoint found no preparation-dependent heterogeneity among six fitted transverse decay rates, with a homogeneity p-value of 0.4003 and a maximum fractional deviation of 2.5%. The result is evidence of consistency with the preregistered NS1 prediction at the stated experimental sensitivity. It is not unique confirmation of SSAF, and it does not exclude state dependence below the achieved resolution. Standard fixed-context open-system quantum mechanics also predicts consistency with this result. The deposited record includes the manuscript, TeX source, submitted Python and notebook protocol, preregistration and preflight records, raw and processed data, machine-readable results, figures, run provenance, licensing information, and checksums. The hardware run was executed on July 17, 2026, with 7,424 shots per effective circuit and 435.0 seconds of QPU usage.
H. Billah and M.M.H. Sarker contributed equally to this work. Interpreting a fixed quantum circuit's output as evidence of a hardware effect requires ruling out two things usually conflated with it: finite-sample fluctuation, and structure already present in the circuit's own noiseless output. Less commonly checked is a third: whether the reference circuit compared against is the one actually executed, once compiler-level qubit routing is accounted for. We execute a fixed 35-qubit, 243-gate diagnostic circuit on IBM Heron-family hardware (three runs, two backends) and show this third check is essential: the routed circuit submitted to hardware has different noiseless predictions than the logical circuit intended, for several qubits. Against the correct, routed-circuit reference, the aggregate deviation is significant in two of three runs, and four registers (0, 9, 14, 27) show a significant output-probability deviation in every run — though we distinguish a high-confidence subset, {0, 9, 27}, with tightly time-matched calibration, from qubit 14, included only on an exploratory basis given its calibration was retrieved roughly two weeks post-execution. Same-backend replicates correlate more strongly by the Pearson measure, though a rank-based (Spearman) test shows this gap does not survive at the level of register ordering, indicating substantial leverage from a small number of registers rather than a broadly robust pattern; these three executions also share a byte-identical payload and are not independent replications in the strictest sense. The mechanism is only partially resolved: independent single-qubit readout error and raw gate count are ruled out as complete explanations for most of these registers, but the simplest version of the leading hypothesis for the single most-affected register does not reproduce the observed cross-backend pattern even with live, backend-specific timing data. A second, structurally different circuit validated only in simulation calibrates the statistical procedure's behavior under one synthetic noise model; it does not itself establish generality to real hardware, and the specific register set found here should not be expected to generalize beyond this study. Note on scope: this is a methodology and case-study contribution centered on executed-circuit references for fixed-circuit diagnostics, not a characterization of IBM Heron hardware in general or a randomized-benchmarking experiment in the formal sense. Supporting data, the routed OpenQASM circuits, raw measurement counts, and analysis code for this study are available on request from the corresponding author. Affiliation: Sonicium Quantum Lab Ltd., Dhaka, Bangladesh.
This archive contains the Version 1 public release of the targeted causal-break testing protocol together with the manuscript, supplementary material, registered experimental protocols, QASM circuits, analysis procedures, and documentation associated with the study. The work demonstrates a low-setting experimental methodology for testing engineered history dependence on superconducting quantum hardware while explicitly preserving preregistration records, failed controls, confirmatory replications, calibration experiments, and protocol revisions.
The Quantum Approximate Optimisation Algorithm is the canonical near-term heuristic, yet on real superconducting hardware its behaviour is set by device physics, not by the algorithm. Hardware demonstrations rarely prove the intended coupling is realised, that genuine entanglement is prepared, or what controls it. We report a pre-registered single-device study on the nine-qubit superconducting processor Red at the Barcelona Supercomputing Center, using its five-qubit component. Across six calibrations we certify bipartite entanglement of a corrected QAOA cost layer on the good coupler at depth one by two-qubit tomographic negativity: 0.077, BCa 95% CI [0.065, 0.091], excluding zero every day, while the coupling-off twin stays separable and the degraded coupler equals zero. We then measure the device physics directly: in a pre-registered manipulation on a fixed Bell preparation (not the QAOA layer), reducing the CZ pulse amplitude causally reduces the certified negativity along a positive, well-fit slope (R^2 = 0.83-0.96), every rung-level interval excluding zero and surviving Holm and Benjamini-Hochberg correction. This is a local linearisation of a peaked response, not a global monotone law: the negativity peaks at conditional phase |zeta| = pi, which the nominal amplitude overshoots. The J=0 twin is a separate off-state control and the fringe visibility is constant, so the effect is coherent. The average gate fidelity is non-monotone in the drive and is reported only as a diagnostic. A per-circuit statevector guardrail excludes a diagonal compilation fault we disclose and repair. A randomized-measurement witness is consistent with entanglement but underpowered. The certificate collapses by depth three, and a pre-registered sixteen-instance depth-three ensemble shows no optimisation signal (one-sided Wilcoxon p = 0.15). We claim no advantage; the instances are classically trivial.
RydbergPhaseDepthQA investigates whether a finite-size witness of the recently established quantum circuit-depth hierarchy mechanism remains experimentally distinguishable after provider compilation and noisy execution on a real quantum processor. The experiment compares a frozen exact (C^7Z) phase-witness circuit with a matched ablation obtained by removing exactly one pre-provider QIS two-qubit layer. The exact circuit has 36 CX gates and two-qubit depth 27, while the ablated circuit has 35 CX gates and depth 26. Hardware execution was performed on IonQ Forte-1 through the Open Quantum platform. An independent confirmatory campaign comprised three exact runs, three matched depth-minus-one runs, and one identity control, with 499 shots per job. The exact implementation achieved a success probability of 0.995992 (95% CI [0.992652, 0.998664]), compared with 0.000668 (95% CI [0, 0.002004]) for the depth-minus-one ablation. The exact-minus-ablation separation was 0.995324, with a 95% lower confidence bound of 0.991316. The identity false-positive probability was 0.002004 (95% CI [0, 0.006012]). All four frozen confirmatory statistical criteria passed, yielding RPDQA_FULL_PASS = True. These results provide a positive finite-size hardware witness of the multi-controlled-phase depth-hierarchy mechanism: for the tested (C^7Z) construction, the experimentally observed separation survives the full path from frozen QIS circuits through provider compilation to noisy QPU execution. The result does not constitute an experimental proof of the complete theoretical (d >= 12) hierarchy, nor does it claim that the final provider-native or pulse-level schedules preserve an exactly one-layer depth difference. The repository includes the frozen circuits, raw hardware results, analysis code, integrity hashes, and reproducibility tools: https://github.com/malikberrada/RydbergPhaseDepthQA
We report forward random-circuit sampling (RCS) on the 120-qubit Nighthawk r2 superconducting processor (ibm_phoenix) with square-lattice connectivity, using 61 qubits, native CZ gates, and the standard cloud execution stack with no benchmark-specific calibration. Two independent fidelity estimators---mirror benchmarking and three- and four-patch cross-entropy benchmarking (XEB)---agree with each other at every measured depth, the mirror from 4 to 40 cycles and the patched estimators from 20 to 40 cycles, across more than two orders of magnitude of fidelity decay, and exceed the first-generation Nighthawk r1 device by more than an order of magnitude at fixed depth. The 36-cycle circuits sit at the depth where tensor-network contraction cost saturates at system size: a contraction-cost estimator validated against the published Sycamore and Zuchongzhi networks places the single-amplitude cost at ∼\sim∼102210^{22}1022 complex operations. At FXEB(36)=2.3×10−3F_{\mathrm{XEB}}(36)=2.3\times10^{-3}FXEB​(36)=2.3×10−3 under favorable memory assumptions this implies 1.2×10271.2\times10^{27}1.2×1027 machine operations within the bounded-fidelity rejection-sampling model --- more than a century of runtime on the Frontier supercomputer --- to collect a 10610^{6}106-sample ensemble, which takes only 19\,s on Nighthawk r2. To our knowledge, this is the first demonstration of quantum advantage for a vanilla random-circuit sampling on a commercially and broadly accessible quantum processor that most non-expert quantum computer users can easily replicate.