Standard device characterization protocols, such as Randomized Benchmarking (RB), typically report averaged, independent error rates per qubit. However, these methods are largely blind to correlated errors between neighbouring qubits: errors that fundamentally break the independent and identically distributed (i.i.d.) noise assumptions relied upon by most quantum error correction (QEC) decoders and error mitigation strategies. In this paper, we present a measurement approach using parity-circuit canaries to estimate pairwise error correlations on noisy intermediate-scale quantum (NISQ) devices. By applying spectral kernel analysis to the resulting correlation matrices, we can quantitatively assess the validity of the independent error assumption. We first validate our approach by emulating the canary protocol on publicly available surface code data from IBM Quantum hardware (ibm_fez). We then extend this proof-of-concept with directly measured, purpose-built canary circuits executed on the same backend, reproduced across independent sessions, controlled for physical adjacency and measurement batching, and shown to be inconsistent with pure estimation noise. The direct measurements confirm a significant, structural spectral violation that is not explained by neighbour-to-neighbour crosstalk alone, is present between arbitrary, chip-wide qubit pairs rather than a specific subset, and reproduces on a second, independent Heron r2 device (ibm_kingston), pointing to a mechanism inherent to the architecture rather than one installation. A three-condition diagnostic further localizes the effect specifically to the two-qubit entangling gate, showing no significant deviation from independence in isolated readout or in simultaneous single-qubit control pulses alone, and a targeted test rules out a simple, load-dependent shared-coupler-electronics mechanism. A circuit-depth scan using repeated entangling gates argues against simple depth-accumulation as the source of the larger violation seen in the original emulated proof-of-concept. Replacing the fixed entangling gate with a continuously parameterized controlled rotation shows that the correlation strength scales with the degree of entanglement produced, not merely with the entangling gate's presence, a relationship that reproduces in direction across three independent Heron r2 devices while varying substantially in absolute magnitude between them. The results also reveal a previously unreported dependence of the excess correlation on the instantaneous marginal error rate, underscoring the need for correlation-aware, dynamically calibrated diagnostics in fault-tolerant quantum computing.
Standard device characterization protocols, such as Randomized Benchmarking (RB), typically report averaged, independent error rates per qubit. However, these methods are largely blind to correlated errors between neighbouring qubits: errors that fundamentally break the independent and identically distributed (i.i.d.) noise assumptions relied upon by most quantum error correction (QEC) decoders and error mitigation strategies. In this paper, we present a measurement approach using parity-circuit canaries to estimate pairwise error correlations on noisy intermediate-scale quantum (NISQ) devices. By applying spectral kernel analysis to the resulting correlation matrices, we can quantitatively assess the validity of the independent error assumption. We first validate our approach by emulating the canary protocol on publicly available surface code data from IBM Quantum hardware (ibm_fez). We then extend this proof-of-concept with directly measured, purpose-built canary circuits executed on the same backend, reproduced across independent sessions, controlled for physical adjacency and measurement batching, and shown to be inconsistent with pure estimation noise. The direct measurements confirm a significant, structural spectral violation that is not explained by neighbour-to-neighbour crosstalk alone, is present between arbitrary, chip-wide qubit pairs rather than a specific subset, and reproduces on a second, independent Heron r2 device (ibm_kingston), pointing to a mechanism inherent to the architecture rather than one installation. A three-condition diagnostic further localizes the effect specifically to the two-qubit entangling gate, showing no significant deviation from independence in isolated readout or in simultaneous single-qubit control pulses alone, and a targeted test rules out a simple, load-dependent shared-coupler-electronics mechanism. A circuit-depth scan using repeated entangling gates argues against simple depth-accumulation as the source of the larger violation seen in the original emulated proof-of-concept. Replacing the fixed entangling gate with a continuously parameterized controlled rotation shows that the correlation strength scales with the degree of entanglement produced, not merely with the entangling gate's presence, a relationship that reproduces in direction across three independent Heron r2 devices while varying substantially in absolute magnitude between them. The results also reveal a previously unreported dependence of the excess correlation on the instantaneous marginal error rate, underscoring the need for correlation-aware, dynamically calibrated diagnostics in fault-tolerant quantum computing.
Abstract We introduce the K–R scaling exponent α, extracted from the three-parameter cost decomposition C = C₀/Kᵅ + R, as a compact diagnostic descriptor of error-accumulation regimes on noisy intermediate-scale quantum (NISQ) hardware. Here, C is the measured circuit infidelity, K is a structural parameter (inverse depth or inverse qubit count), C₀ is the correctable error amplitude, R is the irreducible noise floor, and α quantifies the rate of error accumulation. Through three experimental campaigns totaling approximately 150 circuit executions on two 156-qubit IBM Quantum Heron r2 processors (ibm_kingston and ibm_fez), we observe three distinct scaling regimes: (i) structured scaling with super-linear α in GHZ circuits (α = 1.54–1.64, R² > 0.97) and noise amplification (α = 1.19, R² = 1.000), consistent with correlated multi-qubit errors; (ii) controlled stochastic scaling in Clifford depth and echo circuits (α ≈ 0.5–0.7, R² up to 0.998); and (iii) saturation where α → 0. We organize these results in an (α, R²) phase diagram—the first such empirical diagram for quantum hardware noise—and demonstrate that α serves as a low-cost diagnostic observable enabling regime identification, device fingerprinting, and stability monitoring using fewer than 13 circuits per device. An honest comparison shows that for depth extrapolation, exponential models outperform K–R; however, K–R uniquely provides regime-level insight and device-specific behavioral signatures not accessible from exponential decay rates. By reducing quantum hardware characterization to a small set of experimentally accessible scaling parameters, the K–R framework provides a practical bridge between low-cost benchmarking and physically interpretable noise diagnostics in the NISQ era.
Current advancements in technology have focused the attention of the quantum computing community toward exploring the potential of near-term devices whose computing power surpasses that of classical computers in practical applications. An unresolved central question revolves around whether the inherent noise in these devices can be overcome or whether any potential quantum advantage would be limited. There is no doubt that crosstalk is one of the main sources of noise in noisy intermediate-scale quantum (NISQ) systems, and it poses a fundamental challenge to hardware designs. Crosstalk between parallel instructions can corrupt quantum states and cause incorrect program execution. In this study, we present a necessary analysis of the crosstalk error effect on NISQ devices. Our approach is extremely straightforward and practical to estimate the crosstalk error of various multi-qubit devices. In particular, we combine the randomized benchmarking (RB) and simultaneous randomized benchmarking (SRB) protocol to estimate the crosstalk error from the correlation controlled-NOT (CNOT) gate. We demonstrate this protocol experimentally on 5-, 7-, \& 16-qubit devices. Our results demonstrate the crosstalk error model of three different IBM quantum devices over the experimental week and compare the error variation against the machine, number of qubits, quantum volume, processor, and topology. We then confirm the improvement in the circuit fidelity on different benchmarks by up to 3.06x via inserting an instruction barrier, as compared with an IBM quantum noisy device which offers near-optimal crosstalk mitigation in practice. Finally, we discuss the current system limitation, its tradeoff on fidelity and depth, noise beyond the NISQ system, and mitigation opportunities to ensure that the quantum operation can perform its quantum magic undisturbed.
H. Billah and M.M.H. Sarker contributed equally to this work. Interpreting a fixed quantum circuit's output as evidence of a hardware effect requires ruling out two things usually conflated with it: finite-sample fluctuation, and structure already present in the circuit's own noiseless output. Less commonly checked is a third: whether the reference circuit compared against is the one actually executed, once compiler-level qubit routing is accounted for. We execute a fixed 35-qubit, 243-gate diagnostic circuit on IBM Heron-family hardware (three runs, two backends) and show this third check is essential: the routed circuit submitted to hardware has different noiseless predictions than the logical circuit intended, for several qubits. Against the correct, routed-circuit reference, the aggregate deviation is significant in two of three runs, and four registers (0, 9, 14, 27) show a significant output-probability deviation in every run — though we distinguish a high-confidence subset, {0, 9, 27}, with tightly time-matched calibration, from qubit 14, included only on an exploratory basis given its calibration was retrieved roughly two weeks post-execution. Same-backend replicates correlate more strongly by the Pearson measure, though a rank-based (Spearman) test shows this gap does not survive at the level of register ordering, indicating substantial leverage from a small number of registers rather than a broadly robust pattern; these three executions also share a byte-identical payload and are not independent replications in the strictest sense. The mechanism is only partially resolved: independent single-qubit readout error and raw gate count are ruled out as complete explanations for most of these registers, but the simplest version of the leading hypothesis for the single most-affected register does not reproduce the observed cross-backend pattern even with live, backend-specific timing data. A second, structurally different circuit validated only in simulation calibrates the statistical procedure's behavior under one synthetic noise model; it does not itself establish generality to real hardware, and the specific register set found here should not be expected to generalize beyond this study. Note on scope: this is a methodology and case-study contribution centered on executed-circuit references for fixed-circuit diagnostics, not a characterization of IBM Heron hardware in general or a randomized-benchmarking experiment in the formal sense. Supporting data, the routed OpenQASM circuits, raw measurement counts, and analysis code for this study are available on request from the corresponding author. Affiliation: Sonicium Quantum Lab Ltd., Dhaka, Bangladesh.
Pulse-level calibration metrics — coherence times T₁ and T₂ measured through single-qubit Rabi and Ramsey sequences — are the standard by which quantum hardware providers certify device health. We demonstrate, through 191 circuit executions on three 156-qubit IBM Heron r2 processors (ibm_kingston, ibm_fez, and ibm_marrakesh), that these pulse-level metrics can give opposite conclusions to circuit-level diagnostics on the same device at the same time. Specifically, between experimental sessions on July 3 and July 5, 2026, IBM reported ibm_marrakesh T₂ improved from 303 μs to 340 μs (a 12% improvement), while the K–R scaling exponent α measured from GHZ circuit scaling increased from 1.406 to 3.811 (a 171% increase in coherent error dominance) and GHZ n=2 infidelity rose from 0.018 to 0.204 — a 920% increase in circuit error. We further demonstrate that Ramsey circuit-context T₂ on qubit 0 is approximately 9–30 μs, compared to IBM-reported pulse-level T₂ of 32–340 μs — a discrepancy of 3–11×. We introduce five experimental demonstrations showing K–R circuit-level diagnostics detect degradation invisible to T₁/T₂, provide higher temporal sensitivity, enable algorithm failure prediction, and confirm the theoretical prediction αₜᵥₜᶜʰ + αₑₜₕₒ = 2 within 7% on real hardware. These findings establish circuit-level K–R diagnostics as a necessary complement to pulse-level calibration for operational quantum computing.
The transition from noisy intermediate-scale quantum devices (error rate ∼10−3 ) to fault-tolerant quantum computation (requiring error rates below 10−4 for viable quantum error correction, and approaching 10−5 for practical fault tolerance) is impeded not by any single hardware shortfall but by the way hardware-layer constraints couple across the quantum computing stack. This review offers a blueprint for engineers designing superconducting quantum processors, organized around a three-stage analytical framework applied to five constraints: qubit coherence, gate fidelity, connectivity, readout errors, and crosstalk. The first stage, per-constraint characterization, shows that each constraint’s most severe failure mode generates correlated errors that violate the independence assumptions underlying quantum error correction. The second stage, pairwise interaction analysis, demonstrates that these constraints form a coupled degradation network in which a weakness in one systematically activates and amplifies failures in others, producing compound failure modes invisible to standard isolated benchmarking. The third stage, stack-wide scaling analysis, shows that improving any single constraint unlocks qualitatively different operational regimes only at discrete threshold crossings, so investment planning must target these transitions rather than incremental gains that yield no regime change. Each constraint’s dominant remaining limitation is then classified as either architecturally fundamental, requiring new device physics, or operationally mitigable through software and control advances. The central finding is that correlated error suppression cannot be fully achieved through local optimization, because the same electromagnetic proximity enabling quantum computation also generates the couplings that produce correlated errors. Achieving fault tolerance therefore requires co-design applied simultaneously rather than sequentially.
Noisy qubits pose a fundamental bottleneck for quantum machine learning on near-term hardware, making the characterization of entanglement quality essential. This work uses the Leggett inequalities introduced by Branciard et al. as a probe of bipartite entanglement quality, tested across ideal simulation, noisy simulation, and circuit execution on multiple platforms, including IonQ Forte-1 and IBM Heron R3 Pittsburgh. IonQ Forte-1 demonstrated robust Leggett violations under default transpilation, while IBM Pittsburgh required informed qubit selection to achieve violations. CZ gates on neighboring qubit pairs degraded entanglement correlations on IBM Pittsburgh, even without simultaneous gate execution. For systems that support mid-circuit measurement, the benchmark scales across circuit depth through sequential testing, and parallel singlet pairs extend it across circuit width. The high visibility requirements of the Leggett bound make it a sensitive and lightweight diagnostic for identifying high-quality entanglement resources and detecting correlated errors on quantum hardware.