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arXiv:2606.10114 · IEEE Transactions on Quantum Engineering

A Cryogenic Hybrid Photonic/CMOS Controller Architecture for Scalable Superconducting Qubit Control

Bowen Liu, Zhaoran Rena Huang

quant-phSubmitted Jun 8, 2026• Announced Jun 10, 2026• 0 citations
v1 · Jun 8, 2026v2 · Jun 17, 2026v3 · Sep 1, 2026
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Abstract

Scaling superconducting quantum computers toward thousands of qubits remains a difficult control hardware problem. It requires hardware that reduces room-temperature to cryogenic wiring and cryogenic power while preserving in-fridge programmability for microwave pulse generation. This work develops a 4 K hybrid photonic/CMOS control architecture in which optical fibers distribute shared shaped pulse templates, while local cryogenic CMOS (Cryo-CMOS) circuits provide transmission control, amplitude programming, sample-and-hold envelope shaping, LO-tone and phase selection, and microwave upconversion, enabling both single-qubit and two-qubit gate generation within the same control path. Compared with fully Cryo-CMOS controllers, this architecture reduces per-channel active dissipation by moving high-speed sampled RF/IF waveform synthesis and waveform-memory access out of each cryogenic channel. Compared with purely photonic-link qubit-control approaches, it adds local 4 K programmability for pulse selection, amplitude scaling, timing updates, and LO-phase control, while remaining compatible with room-temperature real-time feedback and quantum error correction (QEC) workflows. We present architecture-level first-order models for 4 K power dissipation, waveform-memory scaling, and controller-induced fidelity limits, and cross-check the dominant fidelity terms using a three-level transmon simulation. The analysis shows that shared optical pulse template distribution with local 4 K envelope programming is a feasible path toward scalable superconducting qubit control.

DOI
10.1109/TQE.2026.3746905
Comments
14 pages, 8 figures. Submitted to IEEE Transactions on Quantum Engineering and under review

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Scaling superconducting quantum computers toward thousands of qubits remains a difficult control hardware problem. It requires hardware that reduces room-temperature to cryogenic wiring and cryogenic power while preserving in-fridge programmability for microwave pulse generation. This work develops a 4 K hybrid photonic/CMOS control architecture in which optical fibers distribute shared shaped pulse templates, while local cryogenic CMOS (Cryo-CMOS) circuits provide transmission control, amplitude programming, sample-and-hold envelope shaping, LO-tone and phase selection, and microwave upconversion, enabling both single-qubit and two-qubit gate generation within the same control path. Compared with fully Cryo-CMOS controllers, this architecture reduces per-channel active dissipation by moving high-speed sampled RF/IF waveform synthesis and waveform-memory access out of each cryogenic channel. Compared with purely photonic-link qubit-control approaches, it adds local 4 K programmability for pulse selection, amplitude scaling, timing updates, and LO-phase control, while remaining compatible with room-temperature real-time feedback and quantum error correction (QEC) workflows. We present architecture-level first-order models for 4 K power dissipation, waveform-memory scaling, and controller-induced fidelity limits, and cross-check the dominant fidelity terms using a three-level transmon simulation. The analysis shows that shared optical pulse template distribution with local 4 K envelope programming is a feasible path toward scalable superconducting qubit control.
Building a large-scale quantum computer requires the co-optimization of both the quantum bits (qubits) and their control electronics. By operating the CMOS control circuits at cryogenic temperatures (cryo-CMOS), and hence in close proximity to the cryogenic solid-state qubits, a compact quantum-computing system can be achieved, thus promising scalability to the large number of qubits required in a practical application. This work presents a cryo-CMOS microwave signal generator for frequency-multiplexed control of 4 × 32 qubits (32 qubits per RF output). A digitally intensive architecture offering full programmability of phase, amplitude, and frequency of the output microwave pulses and a wideband RF front end operating from 2 to 20 GHz allow targeting both spin qubits and transmons. The controller comprises a qubit-phase-tracking direct digital synthesis (DDS) back end for coherent qubit control and a single-sideband (SSB) RF front end optimized for minimum leakage between the qubit channels. Fabricated in Intel 22-nm FinFET technology, it achieves a 48-dB SNR and 45-dB spurious-free dynamic range (SFDR) in a 1-GHz data bandwidth when operating at 3 K, thus enabling high-fidelity qubit control. By exploiting the on-chip 4096-instruction memory, the capability to translate quantum algorithms to microwave signals has been demonstrated by coherently controlling a spin qubit at both 14 and 18 GHz.
Abstract Realizing a practically useful superconducting quantum computer will require a dramatic scale-up of quantum control electronics to meet the growth in required qubit counts. Conventional rack-based room-temperature control electronics impose severe constraints on wiring density, cost, and system footprint, creating a barrier to large-scale and fault-tolerant quantum computing. Here we demonstrate a hybrid quantum control architecture that combines cryogenic complementary metal-oxide semiconductor (cryo‑CMOS) application-specific integrated circuits (ASICs) for two‑qubit flux control with room‑temperature radio‑frequency electronics for single‑qubit control and readout. The resulting system achieves high density and scalable quantum control without compromising two‑qubit gate fidelity. Deployed on a 156‑qubit quantum processor, the cryo-CMOS subsystem achieves two‑qubit gate errors at the {10}^{-3} level, with a best randomized benchmarking error per gate of 8.4\times{10}^{-4}, stable operation over multi‑day timescales, and no measurable performance degradation as we increase the temperature of the cryo-CMOS ASICs from 7 to 20 K. Thermal analysis identifies cryo-CMOS chip operation near 20 K as a favorable regime, enabling efficient cooling of a large number of channels per cryostat. Compared against rack‑based flux-control, the cryo-CMOS subsystem achieves statistically indistinguishable two-qubit gate fidelities under matched gate settings and enables a tenfold improvement in system spatial footprint. These results establish cryo‑CMOS flux control as a practical and scalable foundation for large‑scale and fault-tolerant superconducting quantum systems.
This poster proposes an on-chip optical pulse modulation system for scalable superconducting quantum computers. Towards the scalable design, qubit control systems need to be located in the cryogenic environment to reduce the number of interconnections across the room temperature and the cryogenic regions. The cryogenic CMOS-based qubit control system is a promising approach, yet it is a bottleneck that exhausts the cooling capacity of the dilution refrigerator. In order to eliminate this bottleneck while providing the ability to control multiple quibits with a minimum necessary number of interconnections, this poster extends the RoF (Radio-over-Fiber) system where optical signals are directly fed from the Room Temperature (RT) region to a PD (PhotoDetector) mounted near the transmon qubit through low-loss and high-speed fibers. Unlike the conventional RoF system, the proposed system employs cryogenic silicon photonics-based modulators in the intermediate part for executing gate operations individually at each transmon qubit with a minimum necessary number of fibers across the RT and the cryogenic regions. Evaluation results show that the proposed system eliminates the power consumption by 79.5% compared with the cryogenic CMOS-based design. The proposed system achieves comparable gate fidelity to the control system generating fully customized RF pulses in the RT environment.
A universal fault-tolerant quantum computer will require large-scale control systems that can realize all the waveforms required to implement a gateset that is universal for quantum computing. Optimization of such a system, which must be precise and extensible, is an open research challenge. Here, we present a cryogenic quantum control integrated circuit (IC) that is able to control all the necessary degrees of freedom of a two-qubit subcircuit of a superconducting quantum processor. Specifically, the IC contains a pair of 4–8-GHz RF pulse generators forXYXYXYcontrol, three baseband current generators for qubit and coupler frequency control, and a digital controller that includes a sequencer for gate sequence playback. After motivating the architecture, we describe the circuit-level implementation details and present experimental results. Using standard benchmarking techniques, we show that the cryogenic CMOS (cryo-CMOS) IC is able to execute the components of a gateset that is universal for quantum computing while achieving single-qubitXYXYXYandZZZaverage gate error rates of 0.17%–0.36% and 0.14%–0.17%, respectively, as well as two-qubit average cross-entropy benchmarking (XEB) cycle error rates of 1.2%. These error rates, which were achieved while dissipating just 4 mW/qubit, are comparable to the measured error rates obtained using baseline room-temperature electronics.
Today's hundred-qubit quantum computers require a dramatic scale up to millions of qubits to become practical for solving real-world problems. Although a variety of qubit technologies have been demonstrated, scalability remains a major hurdle. Superconducting (SC) qubits are one of the most mature and promising technologies to overcome this challenge. However, these qubits reside in a millikelvin cryogenic dilution fridge, isolating them from thermal and electrical noise. They are controlled by a rack-full of external electronics through extremely complex wiring and cables. Although thousands of qubits can be fabricated on a single chip and cooled down to millikelvin temperatures, scaling up the control and readout electronics remains an elusive goal. This is mainly due to the limited available cooling power in cryogenic systems constraining the wiring capacity and cabling heat load management. In this article, we focus on scaling up the number of XY-control lines by using cryogenic RF-photonic links. This is one of the major roadblocks to build a thousand qubit superconducting QC. We will first review and study the challenges of state-of-the-art proposed approaches, including cryogenic CMOS and deep-cryogenic photonic methods, to scale up the control interface for SC qubit systems. We will discuss their limitations due to the active power dissipation and passive heat leakage in detail. By analytically modeling the noise sources and thermal budget limits, we will show that our solution can achieve a scale up to a thousand of qubits. Our proposed method can be seamlessly implemented using advanced silicon photonic processes, and the number of required optical fibers can be further reduced by using wavelength division multiplexing (WDM).
As superconducting and silicon-spin quantum processors scale from hundreds to thousands of physical qubits, the interconnect bottleneck between room-temperature classical electronics and mK cryogenic quantum processors poses a critical physical and architectural barrier. Low-latency control loops—essential for Quantum Error Correction (QED), fast reset protocols, and adaptive quantum algorithms—are strictly constrained by thermal load budgets, speed-of-light signal latency across thermal stages, and the bandwidth limits of coax lines. This paper presents a detailed architectural framework for next-generation quantum-classical interfaces. We investigate the transition from traditional, room-temperature arbitrary waveform generators (AWGs) connected via coaxial lines to co-integrated, cryo-CMOS, and single-flux-quantum (SFQ) digital-to-analog and digital signal processing control layers operating directly at the 4 K and 20 mK stages. We evaluate thermal transport, power dissipation, signal attenuation, and physical routing constraints, proposing a heterogeneous hybrid-control topology that satisfies latency budgets below 100 ns while remaining within the tight thermal limits of modern dilution refrigerators.