As superconducting and silicon-spin quantum processors scale from hundreds to thousands of physical qubits, the interconnect bottleneck between room-temperature classical electronics and mK cryogenic quantum processors poses a critical physical and architectural barrier. Low-latency control loops—essential for Quantum Error Correction (QED), fast reset protocols, and adaptive quantum algorithms—are strictly constrained by thermal load budgets, speed-of-light signal latency across thermal stages, and the bandwidth limits of coax lines. This paper presents a detailed architectural framework for next-generation quantum-classical interfaces. We investigate the transition from traditional, room-temperature arbitrary waveform generators (AWGs) connected via coaxial lines to co-integrated, cryo-CMOS, and single-flux-quantum (SFQ) digital-to-analog and digital signal processing control layers operating directly at the 4 K and 20 mK stages. We evaluate thermal transport, power dissipation, signal attenuation, and physical routing constraints, proposing a heterogeneous hybrid-control topology that satisfies latency budgets below 100 ns while remaining within the tight thermal limits of modern dilution refrigerators.
As superconducting and silicon-spin quantum processors scale from hundreds to thousands of physical qubits, the interconnect bottleneck between room-temperature classical electronics and mK cryogenic quantum processors poses a critical physical and architectural barrier. Low-latency control loops—essential for Quantum Error Correction (QED), fast reset protocols, and adaptive quantum algorithms—are strictly constrained by thermal load budgets, speed-of-light signal latency across thermal stages, and the bandwidth limits of coax lines. This paper presents a detailed architectural framework for next-generation quantum-classical interfaces. We investigate the transition from traditional, room-temperature arbitrary waveform generators (AWGs) connected via coaxial lines to co-integrated, cryo-CMOS, and single-flux-quantum (SFQ) digital-to-analog and digital signal processing control layers operating directly at the 4 K and 20 mK stages. We evaluate thermal transport, power dissipation, signal attenuation, and physical routing constraints, proposing a heterogeneous hybrid-control topology that satisfies latency budgets below 100 ns while remaining within the tight thermal limits of modern dilution refrigerators.
Quantum computing promises an exponential speed-up of computation compared to what is nowadays achievable with classical computers. In this way, it enables the evaluation of more complex models and the breaching of current security algorithms. For the operation of a quantum system, many questions remain to be answered. Currently, there are several quantum technologies that promise to be both reliable and scalable, two features required for large scale quantum operations. Common to all technologies is the operating temperature that needs to be close to absolute zero, i.e. below 100 mK, to suppress environment noise and allow the quantum properties to become 'visible'. In order for any quantum processor to be operated, a so-called quantum-classical interface is required for the quantum bit (qubit) read-out and control. This interface consists of various electronic blocks, such as analog-to-digital converters, digital-to-analog converters, mixers, amplifiers and a digital controller. Especially the analog blocks require effort to meet the noise and stability constraints as not to disturb the very sensitive qubits and allow reading of the tiny signals. As the qubits live in extremely deep-cryogenic temperatures, long wires interface the cryogenic with the room temperature environment, where most of the electronics is situated. However, for a scalable system, heat injection becomes a serious problem, with many wires between 300 K and sub-Kelvin. Furthermore, such amount of interconnects is challenging to mechanically place in a dilution refrigerator. Therefore, in this work, we propose to implement the electronics not at room temperature, but at a temperature much closer to the qubits, for example at 4 K. This not only reduces significantly the wiring between room temperature and the qubits, but we can also benefit from lower electronic noise at such a temperature. The operation of conventional electronics almost 200°C below its normal temperature range is not trivial as device properties alter significantly and most circuits no longer operate as intended. In CMOS processes, the main technology in the integrated electronics world, the behaviour of the transistors, required for the implementation of any circuit, deviates considerably at low temperatures. The transistor's threshold voltage goes up, the mobility increases and the subthreshold slope becomes steeper, to name just a few of these deviations. Although there are improvements in performance, there are also some counter effects, and characterization of the transistors is needed to observe the changes. Once devices are characterized at such low temperatures, new models can be built and circuits can be simulated and adapted to operate properly at cryogenic temperatures. Luckily, there are various commercially available devices that can already withstand the chills of cold. We demonstrated various commercially available devices, such as a field-programmable gate array (FPGA) implemented in a 28 nm CMOS process, to be operating without major concerns at 4~K. Its properties alter only slightly, within 5 to 10%, and all tested circuit implementations, working at 300~K, also worked at 4 K. We combined both commercially available devices, that operate 200 K below their specified temperature range, with custom designed CMOS circuits to implement a cryogenic read-out platform for spin qubits. This system comprises amplifiers, an ADC, an FPGA, voltage regulators and a clock generator. It allows to amplify the tiny signal from the qubits and digitize it directly in the FPGA in order to process the data locally at 4~K. This system is one of the first systematic attempts at operating a part of the quantum-classical interface at cryogenic temperatures and forms the basis for future systems comprising the complete electronic interface for qubits to operate at such low temperatures. One of the main problems to tackle for cryogenic electronic systems is their power consumption. Power budgets are simply limited to roughly 1 or 2 Watts at 4 K and exponentially lower at deeper cryogenic temperatures, thus limiting the size of large-scale electronic systems. Our approach of combined commercial and custom circuits will have to be steadily replaced by a single (custom) technology that meets both power and scalability constraints. One of the best candidates is CMOS, a technology that the industry has relied upon for several decades and benefits from many optimizations thanks to Moore's law.
Superconducting qubits are pivotal in advancing quantum computing, poised for scale but limited by the complexity and fidelity of their control and readout systems, relying on RF and signal processing infrastructure. This survey serves as a comprehensive and technically grounded review of control and readout architectures tailored for superconducting qubits. Synthesizing insights from device physics, circuit design, microwave engineering, signal processing, and cryogenic integration, this work details the practicalities of RF pulse generation, signal synthesis, and readout signal analysis for quantum systems. it covers key requirements, parameters, and pulse engineering techniques, including commonly used envelopes like Gaussian and DRAG designs. Moving to the system level, this survey systematically classifies and critically analyses current architectural strategies (covering key areas like frequency conversion, waveform management, and system infrastructure) and technology platforms (including adaptive classical control stacks, cryogenic CMOS circuits, and novel interconnects and interfaces), evaluating their trade-offs in performance. Extensive literature analysis identifies prevailing limitations such as wiring complexity, thermal budget constraints, latency, and power consumption, while highlighting underexplored opportunities for on-chip signal processing and novel interconnects, drawing analogies to advanced communication systems design. By consolidating diverse control paradigms and critically evaluating their trade-offs, this survey provides a unified foundation for designing next-generation quantum control stacks. Finally, a forward-looking roadmap outlines key trends in monolithic integration, cryo-compatible digital architectures, and physics-informed hardware co-design, offering both a retrospective synthesis and a prospective vision for quantum hardware engineering beyond the NISQ era.
Scaling superconducting quantum computers to the fault-tolerant regime calls for a commensurate scaling of the classical control and readout stack. Today's systems largely rely on room-temperature, rack-based instrumentation connected to dilution-refrigerator cryostats through many coaxial cables. Looking ahead, superconducting fault-tolerant quantum computers (FTQCs) will likely adopt a heterogeneous quantum-classical architecture that places selected electronics at cryogenic stages -- for example, cryo-CMOS at 4~K and superconducting digital logic at 4~K and/or mK stages -- to curb wiring and thermal-load overheads. This review distills key requirements, surveys representative room-temperature and cryogenic approaches, and provides a transparent first-order accounting framework for cryoelectronics. Using an RSA-2048-scale benchmark as a concrete reference point, we illustrate how scaling targets motivate constraints on multiplexing and stage-wise cryogenic power, and discuss implications for functional partitioning across room-temperature electronics, cryo-CMOS, and superconducting logic.
In this paper, we provide a system level perspective on the design of control electronics for large scale quantum systems. Quantum computing systems with high-fidelity control and readout, coherent coupling, calibrated gates, and reconfigurable circuits with low error rates are expected to have superior quantum volumes. Cryogenic CMOS plays a crucial role in the realization of scalable quantum computers, by minimizing the feature size, lowering the cost, power consumption, and implementing low latency error correction. Our approach toward achieving scalable feed-back based control systems includes the design of memory based arbitrary waveform generators (AWG’s), wide band radio frequency analog to digital converters, integrated amplifier chain, and state discriminators that can be synchronized with gate sequences. Digitally assisted designs, when implemented in an advanced CMOS node such as 7 nm can reap the benefits of low power due to scaling. A qubit readout chain demands several amplification stages before the digitizer. We propose the co-integration of our in-house developed InP HEMT LNAs with CMOS LNA stages to achieve the required gain at the digitizer input with minimal area. Our approach using high impedance matching between the HEMT LNA and the cryogenic CMOS receiver can relax the design constraints of an inverter-based CMOS LNA, paving the way toward a fully integrated qubit readout chain. The qubit state discriminator consists of a digital signal processor that computes the qubit state from the digitizer output and a pre-determined threshold. The proposed system realizes feedback-based optimal control for error mitigation and reduction of the required data rate through the serial interface to room temperature electronics.
Scaling superconducting quantum computers toward thousands of control channels remains a difficult hardware problem. This requires reducing room-temperature-to-cryogenic interconnects and 4 K power while retaining channel-specific programmability. We develop a hybrid photonic/CMOS control architecture in which optical fibers distribute shared Gaussian and derivative pulse templates, while local cryogenic CMOS circuits provide event-rate amplitude programming, pulse blocking, hold-duration control, photodetection, and microwave upconversion. The architecture supports template-based XY/DRAG control and smooth-edged flat-top envelopes for two-qubit control through separate local signal paths. Compared with full-waveform Cryo-CMOS, it moves high-speed sampled-waveform generation out of each cryogenic channel. Compared with per-channel photonic waveform delivery, it retains a programmable endpoint after optical distribution for applying updated channel coefficients and control states. We evaluate the architecture using post-layout circuit simulations, optical and interconnect models, and system-level power scaling under a common 4 K output boundary. The modeled downlink power is below 1 mW per qubit-control channel at the thousand-channel scale, substantially below the normalized full-waveform Cryo-CMOS result and in the same range as the strict 50-ohm direct-detection WDM reference. Simulated I- and Q-path outputs are propagated through a five-level transmon model, while the simulated sample-and-hold output is evaluated in a coupled-transmon model. The tested single-qubit cases remain below the 10^-3 worst-state error reference, and the representative two-qubit result remains near the same scale after model-level calibration. These results support low-power photonic delivery with limited in-fridge programmability for template-compatible superconducting-qubit control.
Quantum computing promises an exponentially higher computational power than classical computers; although all the building blocks have become available, certain constraints still prevent quantum advantage. The fundamental challenge in building a practical quantum computer is integrating thousands of highly coherent qubits with the control and readout electronics. The need for a high‐coherence qubit drives the effort for quantum error correction algorithms to create fault‐tolerant quantum systems. Error correction becomes tangible in a quantum processor only in large numbers of qubits. Thus, the other challenge is reducing the number of physical interconnects (coaxial lines) between the quantum–classical interface and bulky room‐temperature electronics. To interface thousands of qubits, interconnects can be reduced by bringing the control and readout electronics near the quantum processor. Cryogenic complementary metal–oxide–semiconductor (CMOS) technology has been an ideal candidate for this purpose. Integrated control and readout at cryogenic temperatures require low power dissipation circuit designs and techniques such as frequency‐division multiplexing (FDM) due to the finite cooling power of a dilution refrigerator. Herein, an overview of each building block in a superconducting quantum computer is provided, focusing on scalability. Furthermore, this article is concluded with an outlook discussing current challenges and future directions for the scalable superconducting control and readout.