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arXiv:2606.08873

SCOPE: A Syndrome-Driven Control Plane for QEC-Enabled Quantum Networks

Xiaojie Fan, Zian Wang, Ashutosh Tiwari, Himanshu Gupta

quant-phcs.NISubmitted Jun 7, 2026• Announced Jun 9, 2026• 0 citations
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Abstract

As quantum networks evolve from experimental testbeds to fault-tolerant systems, the primary performance metric shifts from physical link fidelity to end-to-end logical error rate. However, current control planes remain ill-equipped for this transition: routing decisions are typically decoupled from Quantum Error Correction (QEC) strategies, relying on topology or scalar fidelity metrics that fail to predict how specific physical noise structures interact with logical codes. Optimizing this coupled route-and-code performance requires precise, real-time visibility into network error biases, yet traditional active tomography is operationally prohibitive due to throughput collapse and service interruption. We present SCOPE (Syndrome-based COntrol PlanE), a network-layer architecture that enables joint routing and coding optimization using purely passive telemetry. Instead of injecting probes, SCOPE harvests error syndromes -- the parity-check outcomes naturally generated by QEC decoders during user service. By aggregating these signals, SCOPE's inference engine reconstructs the network's time-varying error map, capturing complex, context-dependent noise correlations. This visibility drives a decision engine that proactively pushes optimal route-and-code configurations to source nodes. NetSquid and IBM-calibrated simulations show that SCOPE reduces estimation error by more than 60% relative to a standard EM baseline. In large-scale networks, this precision reduces logical error rates by 30-35% (up to 65%) against topology-aware baselines.

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Abstract: This study investigates a topological quantum error-correction framework for scalable photonic quantum-computing architectures in which fusion-based entangling primitives are combined with tensor-network optimization. The central problem addressed is the gap between high-fidelity photonic components and the stringent logical-error rates required for fault-tolerant quantum computation. Photonic platforms offer room-temperature operation, manufacturable silicon-photonic process flows, high-bandwidth optical interconnects and natural compatibility with measurement-based computation; however, photon loss, probabilistic fusion and decoder latency impose architectural constraints that cannot be resolved by hardware fidelity alone. The proposed framework therefore treats hardware metrics, code geometry and decoding as a coupled optimization problem rather than as separate engineering layers. The manuscript develops a mathematically grounded model of surface-code and cluster-state error correction under photonic loss and fusion noise, then evaluates tensor-network contraction as a decoder and resource-allocation method. The data section explicitly uses published real-data-based benchmark inputs from contemporary photonic and quantum-error-correction literature, supplemented by transparent, domain-plausible projections where complete open photonic logical-QEC datasets are not yet available. Results show that tensor-network optimization improves the logical-error index relative to matching-based baselines in the modelled photonic regime, while the feasibility boundary remains dominated by loss, fusion infidelity and real-time decoding latency. The contribution is a reproducible evaluation framework that links topological protection, photonic architecture constraints and decoder design for future scalable fault-tolerant systems. Keywords: topological quantum error correction; surface code; photonic quantum computing; fusion-based quantum computation; tensor-network decoding; loss tolerance; scalable quantum architecture; measurement-based quantum computing; fault tolerance; silicon photonics.

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Quantum error correction (QEC) is essential for realizing large-scale, fault-tolerant quantum computation, yet its practical implementation remains a major engineering challenge. In particular, QEC demands precise real-time control of a large number of qubits and low-latency, high-throughput and accurate decoding of error syndromes. While most prior work has focused primarily on decoder design, the overall performance of any QEC system depends critically on all its subsystems including control, communication, and decoding, as well as their integration. To address this challenge, we present an open-source, fully integrated QEC system built on RISC-Q, a generator for RISC-V-based quantum control architectures. Implemented on RFSoC FPGAs, our system prototype integrates real-time qubit control, a scalable distributed multi-board architecture, and the state-of-the-art hardware QEC decoder within a low-latency, high-throughput decoding pipeline, forming a complete hardware platform ready for deployment with superconducting qubits. Experimental evaluation on a three-board prototype based on AMD ZCU216 RFSoCs demonstrates an end-to-end QEC decoding-feedback latency of 446 ns for a distance-3 surface code, including syndrome aggregation, network communication, syndrome decoding, and error distribution. Extrapolating from measured subsystem performance and state-of-the-art decoder benchmarks, the architecture can achieve sub-microsecond decoding-feedback latency up to a distance-21 surface code ($\sim$881 physical qubits) when scaled to larger hardware configurations.

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Future quantum networks will enable the interconnection of multiple users distributed across vast geographic distances. Due to these large separations and limited physical resources, communication will often rely on multi-path routing strategies, where physical resources are distributed across channels of varying lengths and delivered to end users. Efficient long-distance quantum communication therefore requires optimizing the allocation of these resources across available paths. In this work, we introduce a performance-oriented approach to quantum network routing by extending the classical concept of Quality of Service (QoS) to the context of multi-path quantum resources distribution. Unlike prior models that consider entanglement generation or quantum memory coherence in isolation, we investigate the interplay between path assignment strategies, coherence time constraints, and quantum error correction (QEC), and how they jointly impact end-to-end communication fidelity. We analyze both unencoded and encoded transmissions over aggregated network paths, quantifying the effects of resource allocation on transmission success. Our findings show that fidelity cannot be optimized independently of memory lifetimes, and that while QEC can enhance performance under specific conditions, it also imposes additional constraints depending on network topology and path-length asymmetries. This work provides a foundation for developing QoS-aware quantum routing protocols that balance fidelity, throughput, and memory utilization -- key considerations for near-term quantum repeater networks.

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Quantum error correction (QEC) is essential for scalable quantum computing. However, it requires classical decoders that are fast and accurate enough to keep pace with quantum hardware. While quantum low-density parity-check codes have recently emerged as a promising route to efficient fault tolerance, current decoding algorithms do not allow one to realize the full potential of these codes in practical settings. Here, we introduce a convolutional neural network decoder that exploits the geometric structure of QEC codes, and use it to probe a novel "waterfall" regime of error suppression, demonstrating that the logical error rates required for large-scale fault-tolerant algorithms are attainable with modest code sizes at current physical error rates, and with latencies within the real-time budgets of several leading hardware platforms. For example, for the $[144, 12, 12]$ Gross code, the decoder achieves logical error rates up to $\sim 17$x below existing decoders - reaching logical error rates $\sim 10^{-10}$ at physical error $p=0.1\%$ - with 3-5 orders of magnitude higher throughput. This decoder also produces well-calibrated confidence estimates that can significantly reduce the time overhead of repeat-until-success protocols. Taken together, these results suggest that the space-time costs associated with fault-tolerant quantum computation may be significantly lower than previously anticipated.

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Scaling quantum networks beyond point-to-point links requires packet forwarding that can tolerate control-plane timing uncertainty. Existing optical-burst switching (OBS) and quantum-wrapper-based packet switching (QW) rely on external classical headers whose jitter-prone processing must remain aligned with in-flight quantum payloads, creating guard-window or fiber-delay-line budget failures. This paper proposes Syndrome-as-Header (SAH), a quantum label-switching architecture that embeds routing labels into the syndrome structure of an encoded payload. The proposed scheme uses Uncorrectable Error Injection (UEI) to map flow labels to reference syndromes and builds a syndrome-space header codebook whose decoding regions remain distinguishable under correctable channel-induced syndrome deviations. Core routers extract the syndrome header, suppress the correctable residual channel-error component, and swap labels without measuring or decoding the logical payload. SAH supports FAST forwarding and VERIFICATION mode, the latter providing end-to-end consistency checking while retaining swappable labels. In NSFNet timing benchmarks with common per-hop quantum error correction (QEC), SAH eliminates the external-header/payload alignment condition, so timing uncertainty appears as memory residence and delivered latency rather than alignment-budget drops. With a $T_2$-based memory-residence penalty, the advantage depends on router memory coherence; for sufficiently long coherence, SAH maintains higher acceptance and throughput than OBS+QEC and QW+QEC under high jitter.

quant-pharXiv:2607.14484•Jul 17, 2026•0 citations
As quantum networks evolve from experimental testbeds to fault-tolerant systems, the primary performance metric shifts from physical link fidelity to end-to-end logical error rate. However, current control planes remain ill-equipped for this transition: routing decisions are typically decoupled from Quantum Error Correction (QEC) strategies, relying on topology or scalar fidelity metrics that fail to predict how specific physical noise structures interact with logical codes. Optimizing this coupled route-and-code performance requires precise, real-time visibility into network error biases, yet traditional active tomography is operationally prohibitive due to throughput collapse and service interruption.
We present SCOPE (Syndrome-based COntrol PlanE), a network-layer architecture that enables joint routing and coding optimization using purely passive telemetry. Instead of injecting probes, SCOPE harvests error syndromes -- the parity-check outcomes naturally generated by QEC decoders during user service. By aggregating these signals, SCOPE's inference engine reconstructs the network's time-varying error map, capturing complex, context-dependent noise correlations. This visibility drives a decision engine that proactively pushes optimal route-and-code configurations to source nodes. NetSquid and IBM-calibrated simulations show that SCOPE reduces estimation error by more than 60% relative to a standard EM baseline. In large-scale networks, this precision reduces logical error rates by 30-35% (up to 65%) against topology-aware baselines.
Abstract: This study investigates a topological quantum error-correction framework for scalable photonic quantum-computing architectures in which fusion-based entangling primitives are combined with tensor-network optimization. The central problem addressed is the gap between high-fidelity photonic components and the stringent logical-error rates required for fault-tolerant quantum computation. Photonic platforms offer room-temperature operation, manufacturable silicon-photonic process flows, high-bandwidth optical interconnects and natural compatibility with measurement-based computation; however, photon loss, probabilistic fusion and decoder latency impose architectural constraints that cannot be resolved by hardware fidelity alone. The proposed framework therefore treats hardware metrics, code geometry and decoding as a coupled optimization problem rather than as separate engineering layers. The manuscript develops a mathematically grounded model of surface-code and cluster-state error correction under photonic loss and fusion noise, then evaluates tensor-network contraction as a decoder and resource-allocation method. The data section explicitly uses published real-data-based benchmark inputs from contemporary photonic and quantum-error-correction literature, supplemented by transparent, domain-plausible projections where complete open photonic logical-QEC datasets are not yet available. Results show that tensor-network optimization improves the logical-error index relative to matching-based baselines in the modelled photonic regime, while the feasibility boundary remains dominated by loss, fusion infidelity and real-time decoding latency. The contribution is a reproducible evaluation framework that links topological protection, photonic architecture constraints and decoder design for future scalable fault-tolerant systems. Keywords: topological quantum error correction; surface code; photonic quantum computing; fusion-based quantum computation; tensor-network decoding; loss tolerance; scalable quantum architecture; measurement-based quantum computing; fault tolerance; silicon photonics.
Quantum error correction (QEC) is essential for realizing large-scale, fault-tolerant quantum computation, yet its practical implementation remains a major engineering challenge. In particular, QEC demands precise real-time control of a large number of qubits and low-latency, high-throughput and accurate decoding of error syndromes. While most prior work has focused primarily on decoder design, the overall performance of any QEC system depends critically on all its subsystems including control, communication, and decoding, as well as their integration. To address this challenge, we present an open-source, fully integrated QEC system built on RISC-Q, a generator for RISC-V-based quantum control architectures. Implemented on RFSoC FPGAs, our system prototype integrates real-time qubit control, a scalable distributed multi-board architecture, and the state-of-the-art hardware QEC decoder within a low-latency, high-throughput decoding pipeline, forming a complete hardware platform ready for deployment with superconducting qubits. Experimental evaluation on a three-board prototype based on AMD ZCU216 RFSoCs demonstrates an end-to-end QEC decoding-feedback latency of 446 ns for a distance-3 surface code, including syndrome aggregation, network communication, syndrome decoding, and error distribution. Extrapolating from measured subsystem performance and state-of-the-art decoder benchmarks, the architecture can achieve sub-microsecond decoding-feedback latency up to a distance-21 surface code ($\sim$881 physical qubits) when scaled to larger hardware configurations.
Future quantum networks will enable the interconnection of multiple users distributed across vast geographic distances. Due to these large separations and limited physical resources, communication will often rely on multi-path routing strategies, where physical resources are distributed across channels of varying lengths and delivered to end users. Efficient long-distance quantum communication therefore requires optimizing the allocation of these resources across available paths. In this work, we introduce a performance-oriented approach to quantum network routing by extending the classical concept of Quality of Service (QoS) to the context of multi-path quantum resources distribution. Unlike prior models that consider entanglement generation or quantum memory coherence in isolation, we investigate the interplay between path assignment strategies, coherence time constraints, and quantum error correction (QEC), and how they jointly impact end-to-end communication fidelity. We analyze both unencoded and encoded transmissions over aggregated network paths, quantifying the effects of resource allocation on transmission success. Our findings show that fidelity cannot be optimized independently of memory lifetimes, and that while QEC can enhance performance under specific conditions, it also imposes additional constraints depending on network topology and path-length asymmetries. This work provides a foundation for developing QoS-aware quantum routing protocols that balance fidelity, throughput, and memory utilization -- key considerations for near-term quantum repeater networks.
Transitioning quantum computing from laboratory physical demonstrations to practical, utility-scale processing requires bridging a multi-order-of-magnitude gap between physical gate fidelities and algorithmic error thresholds. While fault-tolerant quantum computing relies on quantum error correction to span this divide, traditional evaluation metrics focused on isolated physical components fail to reflect real-world execution capacity. In this Perspective, we analyze the physical and microarchitectural bottlenecks governing scalable quantum compute engines: the spatial footprint trade-offs between code encoding efficiency and hardware routing, the temporal latencies of closed-loop decoding under strict cryogenic thermal budgets, and the structural performance asymmetries of modular multi-chip networks. We argue that overcoming these multi-faceted scalability barriers demands moving beyond single-layer hardware optimizations toward a holistic full-stack co-design paradigm—jointly tailoring error-correcting code topologies, control microarchitectures, and interconnect networks to unlock sustainable logical throughput.
Quantum error correction (QEC) is essential for scalable quantum computing. However, it requires classical decoders that are fast and accurate enough to keep pace with quantum hardware. While quantum low-density parity-check codes have recently emerged as a promising route to efficient fault tolerance, current decoding algorithms do not allow one to realize the full potential of these codes in practical settings. Here, we introduce a convolutional neural network decoder that exploits the geometric structure of QEC codes, and use it to probe a novel "waterfall" regime of error suppression, demonstrating that the logical error rates required for large-scale fault-tolerant algorithms are attainable with modest code sizes at current physical error rates, and with latencies within the real-time budgets of several leading hardware platforms. For example, for the [144,12,12][144, 12, 12][144,12,12] Gross code, the decoder achieves logical error rates up to ∼17\sim 17∼17x below existing decoders - reaching logical error rates ∼10−10\sim 10^{-10}∼10−10 at physical error p=0.1%p=0.1\%p=0.1% - with 3-5 orders of magnitude higher throughput. This decoder also produces well-calibrated confidence estimates that can significantly reduce the time overhead of repeat-until-success protocols. Taken together, these results suggest that the space-time costs associated with fault-tolerant quantum computation may be significantly lower than previously anticipated.
Scaling quantum networks beyond point-to-point links requires packet forwarding that can tolerate control-plane timing uncertainty. Existing optical-burst switching (OBS) and quantum-wrapper-based packet switching (QW) rely on external classical headers whose jitter-prone processing must remain aligned with in-flight quantum payloads, creating guard-window or fiber-delay-line budget failures. This paper proposes Syndrome-as-Header (SAH), a quantum label-switching architecture that embeds routing labels into the syndrome structure of an encoded payload. The proposed scheme uses Uncorrectable Error Injection (UEI) to map flow labels to reference syndromes and builds a syndrome-space header codebook whose decoding regions remain distinguishable under correctable channel-induced syndrome deviations. Core routers extract the syndrome header, suppress the correctable residual channel-error component, and swap labels without measuring or decoding the logical payload. SAH supports FAST forwarding and VERIFICATION mode, the latter providing end-to-end consistency checking while retaining swappable labels. In NSFNet timing benchmarks with common per-hop quantum error correction (QEC), SAH eliminates the external-header/payload alignment condition, so timing uncertainty appears as memory residence and delivered latency rather than alignment-budget drops. With a T2T_2T2​-based memory-residence penalty, the advantage depends on router memory coherence; for sufficiently long coherence, SAH maintains higher acceptance and throughput than OBS+QEC and QW+QEC under high jitter.