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arXiv:2607.14484

Syndrome-as-Header: A Quantum Label-Switching Architecture via Uncorrectable Error Injection

IlKwon Sohn, Ju-Bong Kim, Kwangil Bae, Wooyeong Song, Wonhyuk Lee

quant-phSubmitted Jul 16, 2026• Announced Jul 17, 2026• 0 citations
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Abstract

Scaling quantum networks beyond point-to-point links requires packet forwarding that can tolerate control-plane timing uncertainty. Existing optical-burst switching (OBS) and quantum-wrapper-based packet switching (QW) rely on external classical headers whose jitter-prone processing must remain aligned with in-flight quantum payloads, creating guard-window or fiber-delay-line budget failures. This paper proposes Syndrome-as-Header (SAH), a quantum label-switching architecture that embeds routing labels into the syndrome structure of an encoded payload. The proposed scheme uses Uncorrectable Error Injection (UEI) to map flow labels to reference syndromes and builds a syndrome-space header codebook whose decoding regions remain distinguishable under correctable channel-induced syndrome deviations. Core routers extract the syndrome header, suppress the correctable residual channel-error component, and swap labels without measuring or decoding the logical payload. SAH supports FAST forwarding and VERIFICATION mode, the latter providing end-to-end consistency checking while retaining swappable labels. In NSFNet timing benchmarks with common per-hop quantum error correction (QEC), SAH eliminates the external-header/payload alignment condition, so timing uncertainty appears as memory residence and delivered latency rather than alignment-budget drops. With a $T_2$-based memory-residence penalty, the advantage depends on router memory coherence; for sufficiently long coherence, SAH maintains higher acceptance and throughput than OBS+QEC and QW+QEC under high jitter.

Related papers

SCOPE: A Syndrome-Driven Control Plane for QEC-Enabled Quantum Networks

Xiaojie Fan, Zian Wang, Ashutosh Tiwari +1 more

As quantum networks evolve from experimental testbeds to fault-tolerant systems, the primary performance metric shifts from physical link fidelity to end-to-end logical error rate. However, current control planes remain ill-equipped for this transition: routing decisions are typically decoupled from Quantum Error Correction (QEC) strategies, relying on topology or scalar fidelity metrics that fail to predict how specific physical noise structures interact with logical codes. Optimizing this coupled route-and-code performance requires precise, real-time visibility into network error biases, yet traditional active tomography is operationally prohibitive due to throughput collapse and service interruption. We present SCOPE (Syndrome-based COntrol PlanE), a network-layer architecture that enables joint routing and coding optimization using purely passive telemetry. Instead of injecting probes, SCOPE harvests error syndromes -- the parity-check outcomes naturally generated by QEC decoders during user service. By aggregating these signals, SCOPE's inference engine reconstructs the network's time-varying error map, capturing complex, context-dependent noise correlations. This visibility drives a decision engine that proactively pushes optimal route-and-code configurations to source nodes. NetSquid and IBM-calibrated simulations show that SCOPE reduces estimation error by more than 60% relative to a standard EM baseline. In large-scale networks, this precision reduces logical error rates by 30-35% (up to 65%) against topology-aware baselines.

quant-pharXiv:2606.08873•Jun 9, 2026•0 citations

An optical-fibre-integrated buffer for packet-switched quantum networks

Daniel Spegel-Lexne, Joakim Argillander, Martin Clason +5 more

Packet-switched quantum networks require buffers that can delay qubit payloads while routing information is read out in real time. Previous approaches have not provided this functionality in a fully fibre-integrated architecture compatible with telecom infrastructure. Here we demonstrate an optical-fibre-integrated buffer, based on a recirculating loop and a fibre storage line, in which the storage time of a polarisation-encoded qubit payload is determined by readout of an attached packet header. The key component behind this achievement is an ultra-low-loss poled fibre phase modulator, which provides fast, polarisation-insensitive switching directly in fibre and allows header and payload to be processed within the buffer. We demonstrate storage and retrieval of polarisation-encoded qubit payloads for storage times up to 47 $μ$s, with an average quantum bit error rate of 1.8% together with stable operation over several hours. These results establish a practical fibre-based architecture for packet-level quantum network buffering that can easily integrate into the current telecommunication infrastructure opening up new paths for deployment of the quantum internet.

quant-pharXiv:2608.04093•Aug 6, 2026•0 citations

Experimental Demonstration of Datagram Switching With Monitoring in Quantum Wrapper Networks

Mehmet Berkay On, Roberto Proietti, Gamze Gül +4 more

Adapting the architecture and protocols of classical networks to quantum networking is challenging due to the quantum mechanical properties. In this paper, we utilize a Quantum Wrapper Networking architecture that enables transparent and interoperable transportation of quantum wrapper (QW) datagrams, consisting of quantum payloads and classical headers, over optical fiber networks. We experimentally demonstrate end-to-end transportation of QW datagrams in a three-node packet-switched optical network testbed. The header and payload of a QW datagram are multiplexed in time and wavelength, i.e., the 1561.41 nm header precedes the L-band payload. A QW switch/router performs packet switching by reading the headers, generating new headers, and routing the datagrams to their destinations without disturbing quantum information in the payload. We use 20 km fiber links from the source to two distinct destinations in the testbed. Our experiments show$>$22 coincidence-to-accidental ratio (CAR) for both destinations at two different wavelength channels and clear visibility,$>$79%. We further investigate impairments such as chromatic dispersion and wavelength-dependent polarization rotations in the fiber. We observe that the classical headers' bit-error rate (BER) and the quantum payloads' CAR are correlated under the wavelength-independent channel attenuation. Thus, QW network control and management can utilize a type of performance monitoring. We also discuss the QW datagram design constraints and future fast packet switching implementations.

Journal of Lightwave Technology•Feb 5, 2024•8 citations

Real-time decoding of quantum error correction codes using high-performance computing

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Quantum error correction (QEC) is indispensable for building scalable fault-tolerant quantum computers. Effective QEC demands stringent real-time decoding: the decoder must process syndrome measurements and determine corrections within a time scale--typically on the order of microseconds, to avoid data backlog. Scaling to large number of logical qubits further necessitates significant computational resources. In this work, we propose an architecture, called \emph{THQLink}, for real-time decoding of quantum error correction codes using high-performance computing (HPC) resources. The network connecting the HPC and the control system of quantum processing unit (QPU) is built on TH-Express and can be adapted to different quantum technologies and their associated control stacks. We report a round-trip latency of 2.944 $μ$s on average, with an incremental overhead of 130 ns per additional hop. Using a parallel window strategy, we demonstrate real-time decoding (1 $μ$s per QEC round) of the surface code up to distance 19 using a matching-based decoder on CPUs. Our work presents a scalable framework for real-time decoding in fault-tolerant quantum computing. It can be readily applied to quantum-centric supercomputers that feature tight integration between QPU and HPC resources, thereby enabling efficient support for hybrid quantum-classical algorithms and computation-intensive workloads offloaded from the QPU.

quant-pharXiv:2608.03948•Aug 5, 2026•0 citations

AFS: Accurate, Fast, and Scalable Error-Decoding for Fault-Tolerant Quantum Computers

Poulami Das, Christopher A. Pattison, Srilatha Manne +4 more

Quantum computers promise computational advantages for many important problems across various application domains. Unfortunately, physical quantum devices are highly susceptible to errors that limit us from running most of these quantum applications. Quantum Error Correction (QEC) codes are required to implement Fault-Tolerant Quantum Computers (FTQC) on which computations can be performed without encountering errors. Error decoding is a critical component of quantum error correction and is responsible for transforming a set of qubit measurements generated by the QEC code, called the syndrome, into error locations and error types. For the feasibility of implementation, error decoders must not only identify errors with high accuracy, but also be fast and scalable to a large number of qubits. Unfortunately, most of the prior works on error decoding have focused primarily only on the accuracy and have relied on software implementations that are too slow to be of practical use. Furthermore, these studies only look at designing a single decoder and do not analyze the challenges involved in scaling the storage and bandwidth requirements when performing error correction in large systems with thousands of qubits.In this paper, we present AFS, an accurate, fast, and scalable decoder architecture that is designed to operate in the context of systems with hundreds of logical qubits. We present the hardware implementation of AFS, which is based on the Union Find decoding algorithm and employs a three-stage pipelined design. AFS provides orders of magnitude higher accuracy compared to recent SFQ-based hardware decoders (logical error rate of 6×10−10for physical error rate of 10−3) and low decoding latency (42ns on average), while being robust to measurement errors introduced while extracting syndromes during the QEC cycles. We also reduce the amount of decoding hardware required to perform QEC simultaneously on all the logical qubits by co-designing the micro-architecture across multiple decoding units. Our proposed Conjoined-Decoder Architecture (CDA) reduces the storage overhead by 70% (10MB to 2.8MB). Finally, we reduce the bandwidth overheads required to transmit syndromes from the qubits to the decoders by exploiting the sparsity in the syndromes and compressing the data. Our proposed Syndrome Compression reduces the bandwidth requirement by 30x, on an average.

IEEE International Symposium on High-Performance Computer Architecture (HPCA)•Apr 1, 2022•59 citations

Real-Time Quantum Error Correction System Stack: Architecture, Algorithms, and Engineering Practice

Yaojian Chen, Chun-Yang Luan, Peilin Zheng +7 more

Quantum error correction (QEC) is transitioning from physical feasibility demonstrations to systems engineering challenges. Google has achieved below-threshold performance on distance-5/7 surface codes, while Riverlane and Rigetti have demonstrated hardware-integrated low-latency feedback loops. These milestones indicate that the core challenge of real-time decoding has shifted from algorithmic capability to system-level engineering. However, a substantial engineering gap remains between laboratory demonstrations and scalable fault-tolerant quantum computing (FTQC). This white paper addresses three questions: (1) Where are the real bottlenecks in real-time QEC: beyond average decoder speed, the constraints lie in QEC round time, tail latency, and end-to-end data path coordination; (2) How mature are mainstream decoder algorithms: we benchmark the major decoders for both surface codes and quantum low-density parity-check (qLDPC) codes, evaluating their real-time readiness; (3) What system stack do we propose: a six-layer reference architecture from syndrome acquisition to logical operations, with interface definitions and latency budget models. Our results quantify the gap between current decoder performance and real-time requirements, and identify the architectural choices needed to close it.

quant-pharXiv:2605.30765•Jun 1, 2026•0 citations
Scaling quantum networks beyond point-to-point links requires packet forwarding that can tolerate control-plane timing uncertainty. Existing optical-burst switching (OBS) and quantum-wrapper-based packet switching (QW) rely on external classical headers whose jitter-prone processing must remain aligned with in-flight quantum payloads, creating guard-window or fiber-delay-line budget failures. This paper proposes Syndrome-as-Header (SAH), a quantum label-switching architecture that embeds routing labels into the syndrome structure of an encoded payload. The proposed scheme uses Uncorrectable Error Injection (UEI) to map flow labels to reference syndromes and builds a syndrome-space header codebook whose decoding regions remain distinguishable under correctable channel-induced syndrome deviations. Core routers extract the syndrome header, suppress the correctable residual channel-error component, and swap labels without measuring or decoding the logical payload. SAH supports FAST forwarding and VERIFICATION mode, the latter providing end-to-end consistency checking while retaining swappable labels. In NSFNet timing benchmarks with common per-hop quantum error correction (QEC), SAH eliminates the external-header/payload alignment condition, so timing uncertainty appears as memory residence and delivered latency rather than alignment-budget drops. With a T2T_2T2​-based memory-residence penalty, the advantage depends on router memory coherence; for sufficiently long coherence, SAH maintains higher acceptance and throughput than OBS+QEC and QW+QEC under high jitter.
As quantum networks evolve from experimental testbeds to fault-tolerant systems, the primary performance metric shifts from physical link fidelity to end-to-end logical error rate. However, current control planes remain ill-equipped for this transition: routing decisions are typically decoupled from Quantum Error Correction (QEC) strategies, relying on topology or scalar fidelity metrics that fail to predict how specific physical noise structures interact with logical codes. Optimizing this coupled route-and-code performance requires precise, real-time visibility into network error biases, yet traditional active tomography is operationally prohibitive due to throughput collapse and service interruption. We present SCOPE (Syndrome-based COntrol PlanE), a network-layer architecture that enables joint routing and coding optimization using purely passive telemetry. Instead of injecting probes, SCOPE harvests error syndromes -- the parity-check outcomes naturally generated by QEC decoders during user service. By aggregating these signals, SCOPE's inference engine reconstructs the network's time-varying error map, capturing complex, context-dependent noise correlations. This visibility drives a decision engine that proactively pushes optimal route-and-code configurations to source nodes. NetSquid and IBM-calibrated simulations show that SCOPE reduces estimation error by more than 60% relative to a standard EM baseline. In large-scale networks, this precision reduces logical error rates by 30-35% (up to 65%) against topology-aware baselines.
Packet-switched quantum networks require buffers that can delay qubit payloads while routing information is read out in real time. Previous approaches have not provided this functionality in a fully fibre-integrated architecture compatible with telecom infrastructure. Here we demonstrate an optical-fibre-integrated buffer, based on a recirculating loop and a fibre storage line, in which the storage time of a polarisation-encoded qubit payload is determined by readout of an attached packet header. The key component behind this achievement is an ultra-low-loss poled fibre phase modulator, which provides fast, polarisation-insensitive switching directly in fibre and allows header and payload to be processed within the buffer. We demonstrate storage and retrieval of polarisation-encoded qubit payloads for storage times up to 47 μμμs, with an average quantum bit error rate of 1.8% together with stable operation over several hours. These results establish a practical fibre-based architecture for packet-level quantum network buffering that can easily integrate into the current telecommunication infrastructure opening up new paths for deployment of the quantum internet.
Adapting the architecture and protocols of classical networks to quantum networking is challenging due to the quantum mechanical properties. In this paper, we utilize a Quantum Wrapper Networking architecture that enables transparent and interoperable transportation of quantum wrapper (QW) datagrams, consisting of quantum payloads and classical headers, over optical fiber networks. We experimentally demonstrate end-to-end transportation of QW datagrams in a three-node packet-switched optical network testbed. The header and payload of a QW datagram are multiplexed in time and wavelength, i.e., the 1561.41 nm header precedes the L-band payload. A QW switch/router performs packet switching by reading the headers, generating new headers, and routing the datagrams to their destinations without disturbing quantum information in the payload. We use 20 km fiber links from the source to two distinct destinations in the testbed. Our experiments show$>22coincidence−to−accidentalratio(CAR)forbothdestinationsattwodifferentwavelengthchannelsandclearvisibility,22 coincidence-to-accidental ratio (CAR) for both destinations at two different wavelength channels and clear visibility,22coincidence−to−accidentalratio(CAR)forbothdestinationsattwodifferentwavelengthchannelsandclearvisibility,>$79%. We further investigate impairments such as chromatic dispersion and wavelength-dependent polarization rotations in the fiber. We observe that the classical headers' bit-error rate (BER) and the quantum payloads' CAR are correlated under the wavelength-independent channel attenuation. Thus, QW network control and management can utilize a type of performance monitoring. We also discuss the QW datagram design constraints and future fast packet switching implementations.
Quantum error correction (QEC) is indispensable for building scalable fault-tolerant quantum computers. Effective QEC demands stringent real-time decoding: the decoder must process syndrome measurements and determine corrections within a time scale--typically on the order of microseconds, to avoid data backlog. Scaling to large number of logical qubits further necessitates significant computational resources. In this work, we propose an architecture, called \emph{THQLink}, for real-time decoding of quantum error correction codes using high-performance computing (HPC) resources. The network connecting the HPC and the control system of quantum processing unit (QPU) is built on TH-Express and can be adapted to different quantum technologies and their associated control stacks. We report a round-trip latency of 2.944 μμμs on average, with an incremental overhead of 130 ns per additional hop. Using a parallel window strategy, we demonstrate real-time decoding (1 μμμs per QEC round) of the surface code up to distance 19 using a matching-based decoder on CPUs. Our work presents a scalable framework for real-time decoding in fault-tolerant quantum computing. It can be readily applied to quantum-centric supercomputers that feature tight integration between QPU and HPC resources, thereby enabling efficient support for hybrid quantum-classical algorithms and computation-intensive workloads offloaded from the QPU.
Quantum computers promise computational advantages for many important problems across various application domains. Unfortunately, physical quantum devices are highly susceptible to errors that limit us from running most of these quantum applications. Quantum Error Correction (QEC) codes are required to implement Fault-Tolerant Quantum Computers (FTQC) on which computations can be performed without encountering errors. Error decoding is a critical component of quantum error correction and is responsible for transforming a set of qubit measurements generated by the QEC code, called the syndrome, into error locations and error types. For the feasibility of implementation, error decoders must not only identify errors with high accuracy, but also be fast and scalable to a large number of qubits. Unfortunately, most of the prior works on error decoding have focused primarily only on the accuracy and have relied on software implementations that are too slow to be of practical use. Furthermore, these studies only look at designing a single decoder and do not analyze the challenges involved in scaling the storage and bandwidth requirements when performing error correction in large systems with thousands of qubits.In this paper, we present AFS, an accurate, fast, and scalable decoder architecture that is designed to operate in the context of systems with hundreds of logical qubits. We present the hardware implementation of AFS, which is based on the Union Find decoding algorithm and employs a three-stage pipelined design. AFS provides orders of magnitude higher accuracy compared to recent SFQ-based hardware decoders (logical error rate of 6×10−10for physical error rate of 10−3) and low decoding latency (42ns on average), while being robust to measurement errors introduced while extracting syndromes during the QEC cycles. We also reduce the amount of decoding hardware required to perform QEC simultaneously on all the logical qubits by co-designing the micro-architecture across multiple decoding units. Our proposed Conjoined-Decoder Architecture (CDA) reduces the storage overhead by 70% (10MB to 2.8MB). Finally, we reduce the bandwidth overheads required to transmit syndromes from the qubits to the decoders by exploiting the sparsity in the syndromes and compressing the data. Our proposed Syndrome Compression reduces the bandwidth requirement by 30x, on an average.
Quantum error correction (QEC) is transitioning from physical feasibility demonstrations to systems engineering challenges. Google has achieved below-threshold performance on distance-5/7 surface codes, while Riverlane and Rigetti have demonstrated hardware-integrated low-latency feedback loops. These milestones indicate that the core challenge of real-time decoding has shifted from algorithmic capability to system-level engineering. However, a substantial engineering gap remains between laboratory demonstrations and scalable fault-tolerant quantum computing (FTQC). This white paper addresses three questions: (1) Where are the real bottlenecks in real-time QEC: beyond average decoder speed, the constraints lie in QEC round time, tail latency, and end-to-end data path coordination; (2) How mature are mainstream decoder algorithms: we benchmark the major decoders for both surface codes and quantum low-density parity-check (qLDPC) codes, evaluating their real-time readiness; (3) What system stack do we propose: a six-layer reference architecture from syndrome acquisition to logical operations, with interface definitions and latency budget models. Our results quantify the gap between current decoder performance and real-time requirements, and identify the architectural choices needed to close it.