Abstract: This study investigates a topological quantum error-correction framework for scalable photonic quantum-computing architectures in which fusion-based entangling primitives are combined with tensor-network optimization. The central problem addressed is the gap between high-fidelity photonic components and the stringent logical-error rates required for fault-tolerant quantum computation. Photonic platforms offer room-temperature operation, manufacturable silicon-photonic process flows, high-bandwidth optical interconnects and natural compatibility with measurement-based computation; however, photon loss, probabilistic fusion and decoder latency impose architectural constraints that cannot be resolved by hardware fidelity alone. The proposed framework therefore treats hardware metrics, code geometry and decoding as a coupled optimization problem rather than as separate engineering layers. The manuscript develops a mathematically grounded model of surface-code and cluster-state error correction under photonic loss and fusion noise, then evaluates tensor-network contraction as a decoder and resource-allocation method. The data section explicitly uses published real-data-based benchmark inputs from contemporary photonic and quantum-error-correction literature, supplemented by transparent, domain-plausible projections where complete open photonic logical-QEC datasets are not yet available. Results show that tensor-network optimization improves the logical-error index relative to matching-based baselines in the modelled photonic regime, while the feasibility boundary remains dominated by loss, fusion infidelity and real-time decoding latency. The contribution is a reproducible evaluation framework that links topological protection, photonic architecture constraints and decoder design for future scalable fault-tolerant systems. Keywords: topological quantum error correction; surface code; photonic quantum computing; fusion-based quantum computation; tensor-network decoding; loss tolerance; scalable quantum architecture; measurement-based quantum computing; fault tolerance; silicon photonics.
Abstract: This study investigates a topological quantum error-correction framework for scalable photonic quantum-computing architectures in which fusion-based entangling primitives are combined with tensor-network optimization. The central problem addressed is the gap between high-fidelity photonic components and the stringent logical-error rates required for fault-tolerant quantum computation. Photonic platforms offer room-temperature operation, manufacturable silicon-photonic process flows, high-bandwidth optical interconnects and natural compatibility with measurement-based computation; however, photon loss, probabilistic fusion and decoder latency impose architectural constraints that cannot be resolved by hardware fidelity alone. The proposed framework therefore treats hardware metrics, code geometry and decoding as a coupled optimization problem rather than as separate engineering layers. The manuscript develops a mathematically grounded model of surface-code and cluster-state error correction under photonic loss and fusion noise, then evaluates tensor-network contraction as a decoder and resource-allocation method. The data section explicitly uses published real-data-based benchmark inputs from contemporary photonic and quantum-error-correction literature, supplemented by transparent, domain-plausible projections where complete open photonic logical-QEC datasets are not yet available. Results show that tensor-network optimization improves the logical-error index relative to matching-based baselines in the modelled photonic regime, while the feasibility boundary remains dominated by loss, fusion infidelity and real-time decoding latency. The contribution is a reproducible evaluation framework that links topological protection, photonic architecture constraints and decoder design for future scalable fault-tolerant systems. Keywords: topological quantum error correction; surface code; photonic quantum computing; fusion-based quantum computation; tensor-network decoding; loss tolerance; scalable quantum architecture; measurement-based quantum computing; fault tolerance; silicon photonics.
Decoding is an essential component of quantum error correction (QEC), translating stabilizer measurement outcomes into corrective actions that suppress logical errors and preserve logical quantum information. Building fault-tolerant architectures requires increasing the code distance, which in turn places growing demands on decoding accuracy, scalability, and practical deployability. While a wide range of decoding algorithms have been proposed and demonstrated, achieving reliable, scalable, and real-time decoding remains a significant challenge. Machine-learning (ML) approaches are particularly well suited to this setting, as quantum error decoding is fundamentally a problem of processing large volumes of classical data with complex spatiotemporal correlations. This chapter surveys ML-based methods for quantum error decoding, with a focus on topological codes and an emphasis on architectural principles, practical performance, and real-time considerations. We first frame decoding as a learning problem and outline key paradigms, including discriminative, generative, and reinforcement-learning formulations. We then introduce the neural network building blocks that underpin most contemporary neural decoders and discuss how these components can be integrated to balance expressivity, scalability, and latency. Building on this architectural perspective, we review recent progress and benchmarks in neural decoding for memory experiments, and discuss real-time decoding, open challenges, and future directions toward scalable fault-tolerant quantum computing.
Quantum error correction (QEC) is crucial for realizing practical quantum computation. However, the fragility of quantum states to environmental noise poses a significant challenge. This work proposes a novel approach to QEC utilizing topological qubits encoded within photonic networks. Topological qubits, characterized by their robust topological properties, offer inherent protection against local perturbations, making them ideal candidates for QEC. This architecture combines the advantages of both topological protection and the scalability offered by photonic networks. We present a theoretical framework for implementing a specific QEC code based on these principles, detailing the encoding process, error detection, and correction operations. The proposed system demonstrates enhanced resilience to noise compared to traditional qubit implementations. Key performance metrics, such as the surface code's logical error rate, are analyzed, highlighting the potential of this approach for achieving fault-tolerant quantum computation. The core of this method lies in the design of a photonic network tailored to efficiently implement the topological code, addressing limitations encountered in conventional qubit systems. Further investigation explores the impact of network topology and photon loss on the overall performance, proposing strategies for mitigating these effects. This research contributes to the ongoing effort to overcome the challenges of QEC and paves the way for building practical, scalable quantum computers.
Abstract: This study investigates photonic-interconnected quantum chiplets as a modular hardware pathway for scalable and networked quantum computing. The central problem is that monolithic quantum processors face compounding constraints in yield, wiring density, cryogenic routing, interconnect loss, calibration complexity and non-local connectivity. Photonic interconnection offers a technically plausible route to divide a large quantum computer into smaller processors while preserving quantum communication across modules through fibre links, photonic switches, optical transduction or integrated photonic interposers. The paper develops an academically rigorous framework that connects quantum-chiplet architecture, photonic integration, quantum error correction, control latency and manufacturability. It uses secondary real-data anchors from recent public demonstrations and a transparent engineering analysis to evaluate whether modular photonic networking can satisfy requirements for distributed logical qubits, entanglement generation and fault-tolerant operation. Results indicate that photonic chiplets can reduce scaling penalties relative to a monolithic wiring strategy when interconnect loss, feed-forward latency and module yield are jointly optimized. The study concludes that photonic-interconnected chiplets are not a minor packaging improvement but a possible architectural transition comparable to the movement from single-die classical processors to heterogeneous chiplet systems. The strongest contribution is a system-level evaluation model that links physical photonic performance with computer-architecture metrics and identifies the practical thresholds that must be met for Nature-level experimental validation. Keywords quantum computing chips, photonic chiplets, modular quantum computing, quantum interconnects, distributed quantum processors, silicon photonics, quantum networking, fault-tolerant quantum computing, optical interposers, quantum error correction, entanglement routing, wafer-scale quantum manufacturing, cryogenic control, quantum architecture, quantum hardware scalability
As we move towards scalable and modular quantum computing, quantum data centres become imperative. Existing analyses typically treat network constraints in isolation or through simplified models, leaving the interplay between error correction operations and communication resources underexplored. In this work, we present an end-to-end simulation framework that jointly models surface-code operations, internal QPU connectivity, and realistic network constraints including finite entanglement generation rates, limited communication qubits, and bandwidth contention, producing execution latency, from which logical error rate estimates are obtained. The framework is modular by design, allowing individual components such as routing heuristics, scheduling policies, and network topologies to be independently replaced. Numerical evaluation reveals distinct operating regimes in which the optimal resource allocation and code distance selection shift depending on the network characteristics. These results point to tradeoffs in the design of distributed quantum computing architectures that are not visible when computation and communication are modeled separately.
Quantum error correction (QEC) is indispensable for building scalable fault-tolerant quantum computers. Effective QEC demands stringent real-time decoding: the decoder must process syndrome measurements and determine corrections within a time scale--typically on the order of microseconds, to avoid data backlog. Scaling to large number of logical qubits further necessitates significant computational resources. In this work, we propose an architecture, called \emph{THQLink}, for real-time decoding of quantum error correction codes using high-performance computing (HPC) resources. The network connecting the HPC and the control system of quantum processing unit (QPU) is built on TH-Express and can be adapted to different quantum technologies and their associated control stacks. We report a round-trip latency of 2.944 μs on average, with an incremental overhead of 130 ns per additional hop. Using a parallel window strategy, we demonstrate real-time decoding (1 μs per QEC round) of the surface code up to distance 19 using a matching-based decoder on CPUs. Our work presents a scalable framework for real-time decoding in fault-tolerant quantum computing. It can be readily applied to quantum-centric supercomputers that feature tight integration between QPU and HPC resources, thereby enabling efficient support for hybrid quantum-classical algorithms and computation-intensive workloads offloaded from the QPU.
General purpose quantum computers will utilize millions of physical qubits, thus requiring an underlying qubit technology that can be manufactured at scale. Integrated silicon photonics is an intrinsically scalable and manufacturable platform where all necessary gates are available to manipulate qubits, encoded in photons, with very high fidelity and low noise. In this talk, we will discuss architectures for fault-tolerant quantum computing with photonics in the newly-introduced fusion-based quantum computing paradigm. Fusion-based quantum computing presents a new framework for fault-tolerant quantum computation, focused on the efficient integration of quantum error correction and physical-level hardware operations. Its primitives, small entangled resource states and projective entangling gates, make it particularly useful in an integrated photonics platform, offering significant architectural simplifications and reducing requirements on physical level operations.