As we move towards scalable and modular quantum computing, quantum data centres become imperative. Existing analyses typically treat network constraints in isolation or through simplified models, leaving the interplay between error correction operations and communication resources underexplored. In this work, we present an end-to-end simulation framework that jointly models surface-code operations, internal QPU connectivity, and realistic network constraints including finite entanglement generation rates, limited communication qubits, and bandwidth contention, producing execution latency, from which logical error rate estimates are obtained. The framework is modular by design, allowing individual components such as routing heuristics, scheduling policies, and network topologies to be independently replaced. Numerical evaluation reveals distinct operating regimes in which the optimal resource allocation and code distance selection shift depending on the network characteristics. These results point to tradeoffs in the design of distributed quantum computing architectures that are not visible when computation and communication are modeled separately.
As we move towards scalable and modular quantum computing, quantum data centres become imperative. Existing analyses typically treat network constraints in isolation or through simplified models, leaving the interplay between error correction operations and communication resources underexplored. In this work, we present an end-to-end simulation framework that jointly models surface-code operations, internal QPU connectivity, and realistic network constraints including finite entanglement generation rates, limited communication qubits, and bandwidth contention, producing execution latency, from which logical error rate estimates are obtained. The framework is modular by design, allowing individual components such as routing heuristics, scheduling policies, and network topologies to be independently replaced. Numerical evaluation reveals distinct operating regimes in which the optimal resource allocation and code distance selection shift depending on the network characteristics. These results point to tradeoffs in the design of distributed quantum computing architectures that are not visible when computation and communication are modeled separately.
Physical constraints and engineering challenges, including wafer dimensions, classical control cabling, and refrigeration volumes, impose significant limitations on the scalability of quantum computing units. As a result, a modular quantum computing architecture, comprising small processors interconnected by quantum links, is emerging as a promising approach to fault-tolerant quantum computing. However, the requirements that the network must fulfill to enable distributed quantum computation remain largely unexplored. We consider an architecture tailored for qubits with nearest-neighbor physical connectivity, leveraging the surface code for error correction and enabling fault-tolerant operations through lattice surgery and magic state distillation. We propose measurement teleportation as a tool to extend lattice surgery techniques to qubits located on different computing units interconnected via Bell pairs. Through memory simulations, we build an error model for logical operations and deduce an end-to-end resource estimation of Shor’s algorithm over a minimalist distributed architecture. Concretely, for a characteristic physical gate error rate of 10 − 3 , a processor cycle time of 1 µs, factoring a 2048-bit RSA integer is shown to be possible with 379 computing processors, each made with 89 781 qubits, with negligible space and time overhead with respect to a monolithic approach without parallelization, if 70 Bell pairs are available per cycle time between each processor with a fidelity exceeding 98.1 % .
Fault tolerant quantum computation over distributed quantum computing (DQC) platforms requires careful evaluation of resource requirements and noise thresholds. As quantum hardware advances toward modular and networked architectures, various fault tolerant DQC schemes have been proposed, which can be broadly categorized into three architectural types. Type 1 architectures consist of small quantum nodes connected via Greenberger-Horne-Zeilinger (GHZ) states, enabling nonlocal stabilizer measurements. Type 2 architectures distribute a large error correcting code block across multiple modules, with most stabilizer measurements remaining local, except for a small subset at patch boundaries that are performed using nonlocal CNOT gates. Type 3 architectures assign code blocks to distinct modules and can perform fault tolerant operations such as transversal gates, lattice surgery, and teleportation to implement logical operations between code blocks. Using the planar surface code and toric code as representative examples, we analyze how the resource requirements, particularly the number of Bell pairs and the average number of generation attempts, scale with increasing code distance across different architectural designs. This analysis provides valuable insights for identifying architectures well suited to fault tolerant distributed quantum computation under near term hardware and resource constraints.
Modular quantum computing scales quantum systems by connecting Quantum Processing Units (QPUs) through a quantum network. A key challenge in such architectures is efficiently scheduling entanglement generation to enable distributed circuit execution. This work investigates how architectural factors—such as network topology, switch placement, and communication qubit allocation—impact entanglement scheduling and resource utilization. Through simulation, we evaluate static and dynamic scheduling strategies under realistic constraints including probabilistic entanglement generation, limited communication qubits, reconfiguration delays, and qubit coherence time. Our results show that dynamic scheduling performs better in highly connected architectures, while sparse topologies lead to contention and entanglement loss. We also profile Bell State Measurement (BSM) demand to identify architectural bottlenecks and inform provisioning. These insights highlight the critical role of architecture in enabling scalable, efficient distributed quantum computing.
Modular quantum computing is a leading paradigm for scaling quantum computation beyond the resource limitations of monolithic devices. In this architecture, multiple quantum processing units (QPUs), employing identical or distinct qubit modalities, are interconnected via shared entanglement. Here, we investigate how errors at module interfaces and within individual QPUs affect fault-tolerant computation when qubits are encoded using the rotated surface code. Going beyond the logical-memory benchmark, we perform circuit-level simulations of fault-tolerant nonlocal CNOT gates implemented via lattice surgery between QPUs connected by noisy Bell pairs, and analyze the resulting logical error rates. Our results show that interfaces can tolerate noise up to an order of magnitude higher than intra-QPU noise, with only a minor reduction in the fault-tolerance threshold. We further develop an efficient protocol for preparing distributed fault-tolerant logical GHZ states, reducing ancilla overhead, time, and nonlocal Bell-pair consumption. We show that ancilla minimization in this setting is equivalent to a vertex-cover problem on an associated graph, and introduce a polynomial-time heuristic algorithm for finding low-overhead solutions. Our results provide quantitative evidence that distributed quantum error correction can enable scalable, fault-tolerant quantum computation in modular architectures.
Quantum computing promises computational capabilities beyond those of classical systems by exploiting superposition, entanglement, and quantum interference. However, the scalability of current noisy intermediate-scale quantum (NISQ) devices is limited by physical and engineering constraints, restricting the number of available qubits. Distributed quantum computing (DQC) mitigates this limitation by interconnecting multiple quantum processing units (QPUs) via quantum networks capable of distributing high-fidelity entanglement. Realizing such networks requires overcoming probabilistic entanglement generation, finite memory coherence, photon loss, and architectural constraints. This dissertation conducts an in-depth and comprehensive study of resource allocation in quantum networks, aiming to support high-throughput and high-fidelity entanglement distribution over lossy infrastructures. Our work spans the quantum networking stack, from physical-layer entanglement distribution protocols to network planning, quantum storage architectures, and distributed quantum computing. We begin by introducing two asynchronous entanglement distribution protocols-Sequential and Parallel-designed for early-stage quantum networks without global synchronization. Unlike many prior models, our protocols account for classical communication delays and quantum memory decoherence, reflecting practical constraints. Through simulations on real-world topologies such as SURFnet, we show that simple mechanisms such as cutoff-based memory management and sequential asynchronous entanglement distribution protocols can deliver competitive performance while significantly simplifying coordination, narrowing the gap between theoretical proposals and deployable protocols. Next, we formulate quantum network planning as a utility maximization problem that jointly considers entanglement distribution rate and fidelity, treating repeater and memory placement as optimization variables. We propose scalable heuristics and mixed-integer formulations, evaluating them under realistic conditions such as finite coherence time of quantum memories, limited number of memories per repeaters and end nodes, and real network topologies such as ESNet. Our findings offer practical design guidance and highlight how optimal placements depend on underlying physical constraints. To support dynamic workloads and respond to traffic bursts, we propose the Quantum Storage Network (QSN) architecture, where storage nodes buffer EPR pairs in advance of demand as an overlay network. This temporal decoupling improves responsiveness and throughput. Simulations across multiple topologies show that QSNs reduce entanglement distribution service latency by up to 40% and provide improved robustness compared to non-overlay designs, underscoring the value of storage-aware planning in future quantum networks. Finally, we focus on DQC, where large-scale quantum circuits are executed across networked QPUs. We propose a window-based circuit partitioning algorithm that minimizes nonlocal gate execution while balancing load across QPUs. Building on this partitioning, we design an adaptive, dependency-aware entanglement generation scheduler that opportunistically initiates remote entanglement as soon as dependent gates are ready, while accounting for realistic constraints such as coherence limits, probabilistic link generation, and Bell-state measurement (BSM) contention. Applied to benchmark circuits such as QAOA and QFT, this joint approach reduces execution delay by up to 35%. We further perform a two-qubit gate fidelity-sensitivity analysis under to show when the distributed quantum computing can be beneficial. Results show that the number of QPUs significantly impacts sensitivity to non-local gate fidelity: with fewer QPUs, distributed execution can outperform monolithic execution under looser fidelity constraints, whereas with more QPUs, achieving the same advantage requires substantially higher non-local gate fidelities relative to local gate fidelities. These findings identify the parameter regimes in which distributed quantum computing is beneficial, mapping break-even regions (as a function of number of QPUs) and quantifying how much cross-QPU (non-local) gate fidelity must improve—or, equivalently, how much per-QPU local gate fidelity must improve under modularization—for distributed execution to outperform a monolithic baseline. Together, these contributions form a cohesive framework for resource allocation in quantum networks in order to build scalable, delay-tolerant quantum networks and distributed computing systems. By grounding architectural design in realistic physical assumptions, this work advances the state of the art from theoretical modeling to practical, deployable quantum infrastructure.
Abstract Connecting multiple smaller qubit modules by generating high-fidelity entanglement is a promising path for scaling quantum computing hardware. The performance of such a modular quantum computer depends on the quality and rate of entanglement generation. However, identifying optimal architectures and entanglement generation protocols remains an open question. How can modular quantum architectures be designed to achieve fault tolerance while requiring only feasible entanglement rates and hardware? Focusing on solid-state quantum hardware, we investigate the threshold and logical failure rate of a fully distributed surface code. We consider both emission-based and scattering-based entanglement schemes between the modules to link the performance to the physical hardware and identify the regime for fault tolerance. We compare architectures with one or two data qubits per module. For some entanglement schemes, thresholds nearing the thresholds of non-distributed implementations (~ 0.4%) appear feasible with future parameters minimizing the performance gap between modular and monolithic quantum processors.