Quantum computers promise to redefine the boundaries of computational science, offering the potential for exponential speedups in solving complex problems across chemistry, optimization, and materials science. Yet, their practical utility remains constrained by unpredictable performance degradation under real-world noise conditions. A key question is how problem structure itself influences algorithmic resilience. In this work, we present a comprehensive, hardware-aware benchmarking study of the Bernstein-Vazirani algorithm across 11 diverse test patterns on multiple superconducting quantum processors, revealing that algorithmic performance is exquisitely sensitive to problem structure. Our results reveal average success rates of 100.0\% (ideal simulation), 85.2\% (noisy emulation), and 26.4\% (real hardware), representing a dramatic 58.8\% average performance gap between noisy emulation and real hardware execution. With quantum state tomography confirming corresponding average state fidelities of 0.993, 0.760, and a 0.234 fidelity drop to hardware. Performance degrades dramatically from 75.7\% success for sparse patterns to complete failure for high-density 10-qubit patterns. Most strikingly, quantum state tomography reveals a near-perfect correlation between pattern density and state fidelity degradation, providing the fundamental explanation for observed performance patterns. The catastrophic fidelity collapse observed in real hardware measurements -- dropping to 0.111 compared to the predicted 0.763 -- underscores severe limitations in current noise models for capturing structure-dependent error mechanisms. Our work establishes pattern-dependent performance as a critical consideration for quantum algorithm deployment and provides a quantitative framework for predicting algorithm feasibility in practical applications.
Quantum computers promise to redefine the boundaries of computational science, offering the potential for exponential speedups in solving complex problems across chemistry, optimization, and materials science. Yet, their practical utility remains constrained by unpredictable performance degradation under real-world noise conditions. A key question is how problem structure itself influences algorithmic resilience. In this work, we present a comprehensive, hardware-aware benchmarking study of the Bernstein-Vazirani algorithm across 11 diverse test patterns on multiple superconducting quantum processors, revealing that algorithmic performance is exquisitely sensitive to problem structure. Our results reveal average success rates of 100.0% (ideal simulation), 85.2% (noisy emulation), and 26.4% (real hardware), representing a dramatic 58.8% average performance gap between noisy emulation and real hardware execution. With quantum state tomography confirming corresponding average state fidelities of 0.993, 0.760, and a 0.234 fidelity drop to hardware. Performance degrades dramatically from 75.7% success for sparse patterns to complete failure for high-density 10-qubit patterns. Most strikingly, quantum state tomography reveals a near-perfect correlation between pattern density and state fidelity degradation, providing the fundamental explanation for observed performance patterns. The catastrophic fidelity collapse observed in real hardware measurements -- dropping to 0.111 compared to the predicted 0.763 -- underscores severe limitations in current noise models for capturing structure-dependent error mechanisms. Our work establishes pattern-dependent performance as a critical consideration for quantum algorithm deployment and provides a quantitative framework for predicting algorithm feasibility in practical applications.
The performance of quantum algorithms on near-term devices is heavily constrained by hardware noise, yet systematic comparisons of algorithmic vulnerability across diverse noise types remain limited. In this study, we benchmark three representative algorithms: quantum teleportation, Grover’s search, and the Quantum Approximate Optimization Algorithm (QAOA), under depolarizing, amplitude damping, phase damping, and thermal relaxation channels. Using exact density-matrix simulations, we characterize algorithmic performance by evaluating state fidelity decay as a function of noise strength. To enable fair, structure-aware comparisons across circuits of varying depths, we introduce a novel metric, the per-gate decay rate. Our analysis reveals that teleportation exhibits the lowest per-gate vulnerability, whereas Grover’s algorithm demonstrates substantially larger, super-linear decay driven by its repeated oracle–diffuser architecture. QAOA displays intermediate and stable noise resilience across system sizes. Finally, we validate our simulation framework through hardware experiments on an IBM Heron processor, demonstrating strong agreement with theoretical predictions (Pearson’s correlation coefficient r = 0.981). This work establishes a quantitative, structure-aware framework for assessing circuit-level noise sensitivity and offers actionable insights for algorithm selection in the noisy intermediate-scale quantum era.
Cloud-accessible quantum processors enable direct execution of quantum algorithms on heterogeneous hardware platforms. Unlike classical systems, however, identical quantum circuits may exhibit substantially different behavior across devices due to architectural variations in qubit connectivity, gate fidelity, and coherence times.
In this work, we systematically benchmark five representative quantum algorithms - Bell state preparation, GHZ state generation, Quantum Fourier Transform (QFT), Grover's Search, and the Quantum Approximate Optimization Algorithm (QAOA) - across trapped-ion, superconducting, and simulator backends using Amazon Braket. Performance metrics including fidelity, CHSH violation, success probability, circuit depth, and gate counts are evaluated.
Our results demonstrate a strong dependence of algorithmic performance on hardware topology and noise characteristics. For example, 10-qubit GHZ states achieved fidelities above 0.8 on trapped-ion hardware, while superconducting platforms dropped below 0.15 due to routing overhead and accumulated two-qubit gate errors. These findings highlight the importance of hardware-aware algorithm selection and provide practical guidance for benchmarking in the NISQ era.
As quantum processors move into the noisy intermediate-scale quantum (NISQ) era, the central question is no longer whether a quantum algorithm is asymptotically faster than its classical counterpart, but whether it can retain a meaningful speedup under realistic noise, compilation, and measurement constraints. This work develops a quantitative framework for characterizing the noise resilience of quantum advantage. We introduce the advantage robustness function RA(ε), which measures how the asymptotic and concrete performance of an algorithm A degrades with physical error rate ε, and we compute it analytically or numerically for twelve representative algorithm families, including Grover search, amplitude estimation, phase estimation, HHL, VQE/QAOA, Hamiltonian simulation, and sampling algorithms. For each class, we derive critical noise thresholds and depth limits beyond which classical algorithms regain supremacy, explicitly incorporating realistic connectivity and compilation overheads. We show that algorithms based on coherent amplitude amplification are more fragile to coherent errors than depolarizing noise, while variational algorithms display a tradeoff between expressivity and robustness. By combining these algorithm-specific robustness curves with current and projected hardware error rates for superconducting, trapped-ion, neutralatom, and photonic platforms, we map out a phase diagram of practical quantum advantage that links problem size, noise rate, and algorithm type. Our analysis identifies promising near-term application windows in risk analytics, small-molecule chemistry, and structured optimization, and also delineates regions where no advantage is realistic, providing valuable guidance for both algorithm designers and hardware architects.
The Berkeley gate is a high-performance, two-qubit entangling operation with particular potential for quantum error correction and fault-tolerant protocols. However, harnessing this potential on current noisy intermediate-scale quantum (NISQ) processors, requires efficient compilation and robust performance under realistic noise conditions. In this work, we demonstrate a hardware-efficient implementation of the Berkeley gate on a superconducting quantum processor. Using quantum process tomography (QPT), we experimentally characterize its performance and benchmark it against a noiseless quantum simulator to evaluate its practical reliability in the NISQ era. Experimental measurements confirm the gate's correct logical action, producing the target partially entangled state with a subspace confinement probability of [Formula: see text] on real quantum hardware compared to 100% in quantum simulation. Results from QPT experiments show a simulated process fidelity of [Formula: see text], while the experimental process fidelity on hardware is [Formula: see text]. The observed discrepancy is analyzed in the context of device-specific noise sources, including qubit relaxation, dephasing, and state preparation and measurement (SPAM) errors. Our work provides a concrete fidelity benchmark for the Berkeley gate on superconducting hardware and quantify the impact of realistic noise on a non-trivial two-qubit operation, supporting its use in near-term algorithmic and error-correction applications.
Quantum computing is on the cusp of transforming the way we tackle complex problems, and the Grover search algorithm exemplifying its potential to revolutionize the search for unstructured large datasets, offering remarkable speedups over classical methods. Here, we report results for the implementation and characterization of a three-qubit Grover search algorithm using the state-of-the-art scalable quantum computing technology of superconducting quantum architectures. To delve into the algorithm's scalability and performance metrics, our investigation spans the execution of the algorithm across all eight conceivable single-result oracles, alongside nine two-result oracles, employing IBM Quantum's 127-qubit quantum computers. Moreover, we conduct five quantum state tomography experiments to precisely gauge the behavior and efficiency of our implemented algorithm under diverse conditions - ranging from noisy, noise-free environments to the complexities of real-world quantum hardware. By connecting theoretical concepts with real-world experiments, this study not only shed light on the potential of Noisy Intermediate-Scale Quantum Computers in facilitating large-scale database searches but also offer valuable insights into the practical application of the Grover search algorithm in real-world quantum computing applications.
This study examines how noise affects the reliability of quantum circuits through two complementary approaches: a controlled simulation using Qiskit Aer and an execution study on real IBM Quantum hardware. In simulation, five noise models (bit-flip, phase-flip, depolarizing, readout, and thermal-relaxation) were applied to a parameterized benchmark circuit across varying qubit counts, circuit depths, and noise strengths, producing 6,000 experimental observations. Success probability declined substantially as qubit count and circuit depth increased, with bit-flip, phase-flip, and depolarizing noise degrading performance far more severely (mean success probabilities of 0.597, 0.580, and 0.607) than readout noise (0.917) or thermal-relaxation noise (0.982). The same benchmark circuit was then executed on the ibm_marrakesh processor across 150 hardware runs (150,000 shots). Hardware performance remained consistently high (mean success probability 0.992), declining with qubit count (0.998 at two qubits to 0.986 at six) but showing little sensitivity to circuit depth. These results indicate that controlled noise mechanisms and real hardware degrade circuit performance through different dynamics, with implications for interpreting simulated noise models relative to physical device behavior.