This study examines how noise affects the reliability of quantum circuits through two complementary approaches: a controlled simulation using Qiskit Aer and an execution study on real IBM Quantum hardware. In simulation, five noise models (bit-flip, phase-flip, depolarizing, readout, and thermal-relaxation) were applied to a parameterized benchmark circuit across varying qubit counts, circuit depths, and noise strengths, producing 6,000 experimental observations. Success probability declined substantially as qubit count and circuit depth increased, with bit-flip, phase-flip, and depolarizing noise degrading performance far more severely (mean success probabilities of 0.597, 0.580, and 0.607) than readout noise (0.917) or thermal-relaxation noise (0.982). The same benchmark circuit was then executed on the ibm_marrakesh processor across 150 hardware runs (150,000 shots). Hardware performance remained consistently high (mean success probability 0.992), declining with qubit count (0.998 at two qubits to 0.986 at six) but showing little sensitivity to circuit depth. These results indicate that controlled noise mechanisms and real hardware degrade circuit performance through different dynamics, with implications for interpreting simulated noise models relative to physical device behavior.
This study examines how noise affects the reliability of quantum circuits through two complementary approaches: a controlled simulation using Qiskit Aer and an execution study on real IBM Quantum hardware. In simulation, five noise models (bit-flip, phase-flip, depolarizing, readout, and thermal-relaxation) were applied to a parameterized benchmark circuit across varying qubit counts, circuit depths, and noise strengths, producing 6,000 experimental observations. Success probability declined substantially as qubit count and circuit depth increased, with bit-flip, phase-flip, and depolarizing noise degrading performance far more severely (mean success probabilities of 0.597, 0.580, and 0.607) than readout noise (0.917) or thermal-relaxation noise (0.982). The same benchmark circuit was then executed on the ibm_marrakesh processor across 150 hardware runs (150,000 shots). Hardware performance remained consistently high (mean success probability 0.992), declining with qubit count (0.998 at two qubits to 0.986 at six) but showing little sensitivity to circuit depth. These results indicate that controlled noise mechanisms and real hardware degrade circuit performance through different dynamics, with implications for interpreting simulated noise models relative to physical device behavior.
Abstract This practical guide presents methods for constructing noise models using the Qiskit Aer noise module within the IBM Q ecosystem. The objective is to simulate quantum circuits under realistic error conditions, enabling accurate emulation of noisy quantum processors. The guide demonstrates how to: Use the Qiskit Aer noise module to define custom noise models. Incorporate gate errors, readout errors, and decoherence effects into simulations. Apply noise channels (e.g., depolarizing, amplitude damping, phase damping). Attach noise models to quantum circuit simulations. Analyze how noise affects algorithm performance and output distributions. Building noise models is essential for studying the behavior of quantum algorithms in the NISQ (Noisy Intermediate-Scale Quantum) era. It allows researchers to evaluate algorithm robustness, optimize circuit depth, and test error mitigation strategies before execution on real IBM Quantum hardware. This approach provides a bridge between ideal theoretical circuits and physically realistic quantum devices, enhancing the reliability and applicability of quantum computing experiments.
Quantum counters are very crucial elements in the design of quantum sequential circuits and quantum control systems. This article details the design, implementation, and noise-aware benchmarking of large-scale quantum counter designs based on the Qiskit framework and IBM Quantum computing platforms. The quantum counter architectures introduced are 2-bit, 3-bit, 4-bit, and 5-bit quantum counters which are developed using reversible quantum gates like Pauli-X, Controlled-NOT (CNOT), Toffoli, and Multi-Controlled X (MCX) gates. Firstly, all the counter architectures were confirmed to be working well in the ideal simulation scenario using the Qiskit Aer simulator where they achieved perfect computational fidelity and produced correct counting sequences. For the assessment of practical performance in the Noisy Intermediate-Scale Quantum (NISQ) environment, several quantum noise models, including bit-flip noise, depolarizing noise, amplitude damping noise, and phase damping noise, were introduced within the experimental framework. The experimental findings indicate that as circuits become more complex, the precision of computations decreases in the presence of real-world noise conditions. Under bit-flip noise, the correct counts noted changed from 846 for the 2-bit counter to 620 for the 5-bit counter. Likewise, depolarizing noise led to a slight decline, whereas amplitude damping noise resulted in the most drastic decrease in performance, dropping the correct counts from 253 in the 2-bit design to merely 33 in the 5-bit design. On the contrary, a phase damping noise showed almost no impact and retained 1024 correct counts across all architectures. The scalability analysis demonstrates that quantum counter architectures based on reversible gates can proficiently work over quite extensive qubit configurations while maintaining functional correctness. Nevertheless, the increase in circuit depth and gate complexity mainly results in susceptibility to decoherence and noise accumulation. This work offers a unified framework for the development and evaluation of large-scale quantum sequential circuits and sheds light on building quantum systems that can be used fault-tolerantly in future quantum computing implementations.
Fault-tolerant quantum computation requires quantum error correction (QEC), and while the performance of various QEC codes has been well characterized under idealized noise conditions, it has not been sufficiently characterized by simulation under realistic noise conditions.In this paper, the performance of three basic QEC codes (3-qubit Bit-Flip, 3-qubit Phase-Flip and Shor's 9-qubit [[9,1,3]]) under simulated depolarizing noise, by using Qiskit Aer, is analyzed systematically in three stages.Stage 1 is a validation of all three implementations under ideal circumstances.Stage 2 tests for 6 different error rates of 0% to 5%, and runs 2048 shots per error rate.Stage 3 brings the analysis from stage 2 to 0% to 10%, but with an uncorrected baseline for comparison.Results verify that Shor's > Bit-Flip > Phase-Flip is consistent over practically relevant error rates.At 1% noise, within current IBM Quantum hardware range, all three codes achieve a logical fidelity of over 98.7%.An error rate of 7-8% is used to identify a cross-over threshold above which the simpler Bit-Flip code can match Shor's code in fidelity with only one-third the number of qubits.
Abstract Quantum noise, typically considered an obstacle in quantum computing, provides novel prospects in random number generation. This research investigates the possibility of several forms of quantum noise as significant resources for producing high-quality randomness. The study employed simulations of random quantum circuits to examine the effects of bit-flips, phase-flips, and depolarizing noise at different intensities. We conducted the simulations in a controlled setting using the Qiskit Aer simulator, which we selected for its ability to accurately mimic noise effects and replicate the behaviour of actual quantum gear. The research indicated that bit-flip and depolarizing noise consistently produced more significant amounts of unpredictability than phase-flip and noiseless circuits. Applying the produced binary sequences to the NIST Statistical Test Suite corroborated the discovery, confirming their superior quality and appropriateness for applications requiring random numbers. The study suggests that we can efficiently use quantum noise to create safe randomness, which offers significant benefits for encryption, simulations, and other domains that demand genuine unpredictability.
Cloud-accessible quantum processors enable direct execution of quantum algorithms on heterogeneous hardware platforms. Unlike classical systems, however, identical quantum circuits may exhibit substantially different behavior across devices due to architectural variations in qubit connectivity, gate fidelity, and coherence times.
In this work, we systematically benchmark five representative quantum algorithms - Bell state preparation, GHZ state generation, Quantum Fourier Transform (QFT), Grover's Search, and the Quantum Approximate Optimization Algorithm (QAOA) - across trapped-ion, superconducting, and simulator backends using Amazon Braket. Performance metrics including fidelity, CHSH violation, success probability, circuit depth, and gate counts are evaluated.
Our results demonstrate a strong dependence of algorithmic performance on hardware topology and noise characteristics. For example, 10-qubit GHZ states achieved fidelities above 0.8 on trapped-ion hardware, while superconducting platforms dropped below 0.15 due to routing overhead and accumulated two-qubit gate errors. These findings highlight the importance of hardware-aware algorithm selection and provide practical guidance for benchmarking in the NISQ era.
The performance of quantum algorithms on near-term devices is heavily constrained by hardware noise, yet systematic comparisons of algorithmic vulnerability across diverse noise types remain limited. In this study, we benchmark three representative algorithms: quantum teleportation, Grover’s search, and the Quantum Approximate Optimization Algorithm (QAOA), under depolarizing, amplitude damping, phase damping, and thermal relaxation channels. Using exact density-matrix simulations, we characterize algorithmic performance by evaluating state fidelity decay as a function of noise strength. To enable fair, structure-aware comparisons across circuits of varying depths, we introduce a novel metric, the per-gate decay rate. Our analysis reveals that teleportation exhibits the lowest per-gate vulnerability, whereas Grover’s algorithm demonstrates substantially larger, super-linear decay driven by its repeated oracle–diffuser architecture. QAOA displays intermediate and stable noise resilience across system sizes. Finally, we validate our simulation framework through hardware experiments on an IBM Heron processor, demonstrating strong agreement with theoretical predictions (Pearson’s correlation coefficient r = 0.981). This work establishes a quantitative, structure-aware framework for assessing circuit-level noise sensitivity and offers actionable insights for algorithm selection in the noisy intermediate-scale quantum era.