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International Conference on Networks, Computers and Communications (ICNCCom)

Noise-Aware Design of Quantum Counters Using Qiskit and IBM Quantum Processors

E Mahesh, K Raju

Published Jul 1, 2026• 0 citations
Publisher
DOI
10.1109/icnccom69117.2026.11736261

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Quantum counters are very crucial elements in the design of quantum sequential circuits and quantum control systems. This article details the design, implementation, and noise-aware benchmarking of large-scale quantum counter designs based on the Qiskit framework and IBM Quantum computing platforms. The quantum counter architectures introduced are 2-bit, 3-bit, 4-bit, and 5-bit quantum counters which are developed using reversible quantum gates like Pauli-X, Controlled-NOT (CNOT), Toffoli, and Multi-Controlled X (MCX) gates. Firstly, all the counter architectures were confirmed to be working well in the ideal simulation scenario using the Qiskit Aer simulator where they achieved perfect computational fidelity and produced correct counting sequences. For the assessment of practical performance in the Noisy Intermediate-Scale Quantum (NISQ) environment, several quantum noise models, including bit-flip noise, depolarizing noise, amplitude damping noise, and phase damping noise, were introduced within the experimental framework. The experimental findings indicate that as circuits become more complex, the precision of computations decreases in the presence of real-world noise conditions. Under bit-flip noise, the correct counts noted changed from 846 for the 2-bit counter to 620 for the 5-bit counter. Likewise, depolarizing noise led to a slight decline, whereas amplitude damping noise resulted in the most drastic decrease in performance, dropping the correct counts from 253 in the 2-bit design to merely 33 in the 5-bit design. On the contrary, a phase damping noise showed almost no impact and retained 1024 correct counts across all architectures. The scalability analysis demonstrates that quantum counter architectures based on reversible gates can proficiently work over quite extensive qubit configurations while maintaining functional correctness. Nevertheless, the increase in circuit depth and gate complexity mainly results in susceptibility to decoherence and noise accumulation. This work offers a unified framework for the development and evaluation of large-scale quantum sequential circuits and sheds light on building quantum systems that can be used fault-tolerantly in future quantum computing implementations.

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Quantum counters are very crucial elements in the design of quantum sequential circuits and quantum control systems. This article details the design, implementation, and noise-aware benchmarking of large-scale quantum counter designs based on the Qiskit framework and IBM Quantum computing platforms. The quantum counter architectures introduced are 2-bit, 3-bit, 4-bit, and 5-bit quantum counters which are developed using reversible quantum gates like Pauli-X, Controlled-NOT (CNOT), Toffoli, and Multi-Controlled X (MCX) gates. Firstly, all the counter architectures were confirmed to be working well in the ideal simulation scenario using the Qiskit Aer simulator where they achieved perfect computational fidelity and produced correct counting sequences. For the assessment of practical performance in the Noisy Intermediate-Scale Quantum (NISQ) environment, several quantum noise models, including bit-flip noise, depolarizing noise, amplitude damping noise, and phase damping noise, were introduced within the experimental framework. The experimental findings indicate that as circuits become more complex, the precision of computations decreases in the presence of real-world noise conditions. Under bit-flip noise, the correct counts noted changed from 846 for the 2-bit counter to 620 for the 5-bit counter. Likewise, depolarizing noise led to a slight decline, whereas amplitude damping noise resulted in the most drastic decrease in performance, dropping the correct counts from 253 in the 2-bit design to merely 33 in the 5-bit design. On the contrary, a phase damping noise showed almost no impact and retained 1024 correct counts across all architectures. The scalability analysis demonstrates that quantum counter architectures based on reversible gates can proficiently work over quite extensive qubit configurations while maintaining functional correctness. Nevertheless, the increase in circuit depth and gate complexity mainly results in susceptibility to decoherence and noise accumulation. This work offers a unified framework for the development and evaluation of large-scale quantum sequential circuits and sheds light on building quantum systems that can be used fault-tolerantly in future quantum computing implementations.
We experimentally study error mitigation and finite-shot sampling on superconducting quantum hardware under a constrained execution budget. The study combines calibration-aware qubit selection, circuit-depth scaling, zero-noise extrapolation, dynamical decoupling, readout-error mitigation, and repeated-shot estimation on an IBM Quantum processor. Experiments are organized across ideal simulation, noise-model simulation, and physical-device execution to separate sampling uncertainty from device-induced error. We investigate how mitigation performance changes with circuit depth, effective noise scale, qubit connectivity, and measurement budget, and quantify accuracy using expectation-value error, mean-squared error, statistical uncertainty, and mitigation gain. A fixed hardware-execution budget is used to evaluate shot allocation strategies and repeated measurements without relying on unlimited sampling. The resulting analysis provides a hardware-aware characterization of when mitigation improves expectation-value estimation and when finite-shot fluctuations offset the benefit of additional mitigation overhead. The implementation uses contemporary Qiskit and IBM Quantum Runtime workflows and is designed to provide reproducible experimental evidence for error-mitigation studies on current quantum processors.
Quantum processors are being integrated into HPC ecosystems as co-processors, where compilation of quantum circuits into hardware-executable form determines both output fidelity and runtime. Current compilers use a fixed pass sequence and ignore the fact that optimal pass selection varies with circuit, hardware, and noise conditions. We present TuniQ, a reinforcement learning-based system that selects compilation passes at each pipeline stage, adapting to circuit, backend, and current noise profile. TuniQ introduces several novel design components like a dual-encoder for stage-aware representation, shaped rewards for cross-stage credit assignment, and dynamic action masking for valid compilation. Evaluated across diverse quantum workloads on multiple IBM Quantum Cloud processors, TuniQ improves fidelity and reduces compilation time over the state-of-the-art IBM Qiskit transpiler, generalizes across backends without retraining, and scales strongly to utility-scale circuits with growing advantage.