Quantum counters are very crucial elements in the design of quantum sequential circuits and quantum control systems. This article details the design, implementation, and noise-aware benchmarking of large-scale quantum counter designs based on the Qiskit framework and IBM Quantum computing platforms. The quantum counter architectures introduced are 2-bit, 3-bit, 4-bit, and 5-bit quantum counters which are developed using reversible quantum gates like Pauli-X, Controlled-NOT (CNOT), Toffoli, and Multi-Controlled X (MCX) gates. Firstly, all the counter architectures were confirmed to be working well in the ideal simulation scenario using the Qiskit Aer simulator where they achieved perfect computational fidelity and produced correct counting sequences. For the assessment of practical performance in the Noisy Intermediate-Scale Quantum (NISQ) environment, several quantum noise models, including bit-flip noise, depolarizing noise, amplitude damping noise, and phase damping noise, were introduced within the experimental framework. The experimental findings indicate that as circuits become more complex, the precision of computations decreases in the presence of real-world noise conditions. Under bit-flip noise, the correct counts noted changed from 846 for the 2-bit counter to 620 for the 5-bit counter. Likewise, depolarizing noise led to a slight decline, whereas amplitude damping noise resulted in the most drastic decrease in performance, dropping the correct counts from 253 in the 2-bit design to merely 33 in the 5-bit design. On the contrary, a phase damping noise showed almost no impact and retained 1024 correct counts across all architectures. The scalability analysis demonstrates that quantum counter architectures based on reversible gates can proficiently work over quite extensive qubit configurations while maintaining functional correctness. Nevertheless, the increase in circuit depth and gate complexity mainly results in susceptibility to decoherence and noise accumulation. This work offers a unified framework for the development and evaluation of large-scale quantum sequential circuits and sheds light on building quantum systems that can be used fault-tolerantly in future quantum computing implementations.
Quantum counters are very crucial elements in the design of quantum sequential circuits and quantum control systems. This article details the design, implementation, and noise-aware benchmarking of large-scale quantum counter designs based on the Qiskit framework and IBM Quantum computing platforms. The quantum counter architectures introduced are 2-bit, 3-bit, 4-bit, and 5-bit quantum counters which are developed using reversible quantum gates like Pauli-X, Controlled-NOT (CNOT), Toffoli, and Multi-Controlled X (MCX) gates. Firstly, all the counter architectures were confirmed to be working well in the ideal simulation scenario using the Qiskit Aer simulator where they achieved perfect computational fidelity and produced correct counting sequences. For the assessment of practical performance in the Noisy Intermediate-Scale Quantum (NISQ) environment, several quantum noise models, including bit-flip noise, depolarizing noise, amplitude damping noise, and phase damping noise, were introduced within the experimental framework. The experimental findings indicate that as circuits become more complex, the precision of computations decreases in the presence of real-world noise conditions. Under bit-flip noise, the correct counts noted changed from 846 for the 2-bit counter to 620 for the 5-bit counter. Likewise, depolarizing noise led to a slight decline, whereas amplitude damping noise resulted in the most drastic decrease in performance, dropping the correct counts from 253 in the 2-bit design to merely 33 in the 5-bit design. On the contrary, a phase damping noise showed almost no impact and retained 1024 correct counts across all architectures. The scalability analysis demonstrates that quantum counter architectures based on reversible gates can proficiently work over quite extensive qubit configurations while maintaining functional correctness. Nevertheless, the increase in circuit depth and gate complexity mainly results in susceptibility to decoherence and noise accumulation. This work offers a unified framework for the development and evaluation of large-scale quantum sequential circuits and sheds light on building quantum systems that can be used fault-tolerantly in future quantum computing implementations.
This study examines how noise affects the reliability of quantum circuits through two complementary approaches: a controlled simulation using Qiskit Aer and an execution study on real IBM Quantum hardware. In simulation, five noise models (bit-flip, phase-flip, depolarizing, readout, and thermal-relaxation) were applied to a parameterized benchmark circuit across varying qubit counts, circuit depths, and noise strengths, producing 6,000 experimental observations. Success probability declined substantially as qubit count and circuit depth increased, with bit-flip, phase-flip, and depolarizing noise degrading performance far more severely (mean success probabilities of 0.597, 0.580, and 0.607) than readout noise (0.917) or thermal-relaxation noise (0.982). The same benchmark circuit was then executed on the ibm_marrakesh processor across 150 hardware runs (150,000 shots). Hardware performance remained consistently high (mean success probability 0.992), declining with qubit count (0.998 at two qubits to 0.986 at six) but showing little sensitivity to circuit depth. These results indicate that controlled noise mechanisms and real hardware degrade circuit performance through different dynamics, with implications for interpreting simulated noise models relative to physical device behavior.
Abstract This practical guide presents methods for constructing noise models using the Qiskit Aer noise module within the IBM Q ecosystem. The objective is to simulate quantum circuits under realistic error conditions, enabling accurate emulation of noisy quantum processors. The guide demonstrates how to: Use the Qiskit Aer noise module to define custom noise models. Incorporate gate errors, readout errors, and decoherence effects into simulations. Apply noise channels (e.g., depolarizing, amplitude damping, phase damping). Attach noise models to quantum circuit simulations. Analyze how noise affects algorithm performance and output distributions. Building noise models is essential for studying the behavior of quantum algorithms in the NISQ (Noisy Intermediate-Scale Quantum) era. It allows researchers to evaluate algorithm robustness, optimize circuit depth, and test error mitigation strategies before execution on real IBM Quantum hardware. This approach provides a bridge between ideal theoretical circuits and physically realistic quantum devices, enhancing the reliability and applicability of quantum computing experiments.
The "Noisy intermediate-scale quantum" NISQ machine era primarily focuses on mitigating noise, controlling errors, and executing high-fidelity operations, hence requiring shallow circuit depth and noise robustness. Approximate computing is a novel computing paradigm that produces imprecise results by relaxing the need for fully precise output for error-tolerant applications including multimedia, data mining, and image processing. We investigate how approximate computing can improve the noise resilience of quantum adder circuits in NISQ quantum computing. We propose five designs of approximate quantum adders to reduce depth while making them noise-resilient, in which three designs are with carryout, while two are without carryout. We have used novel design approaches that include approximating the Sum only from the inputs (pass-through designs) and having zero depth, as they need no quantum gates. The second design style uses a single CNOT gate to approximate the SUM with a constant depth of O(1). We performed our experimentation on IBM Qiskit on noise models including thermal, depolarizing, amplitude damping, phase damping, and bitflip: (i) Compared to exact quantum ripple carry adder without carryout the proposed approximate adders without carryout have improved fidelity ranging from 8.34% to 219.22%, and (ii) Compared to exact quantum ripple carry adder with carryout the proposed approximate adders with carryout have improved fidelity ranging from 8.23% to 371%. Further, the proposed approximate quantum adders are evaluated in terms of various error metrics.
Approximate quantum adders are gaining traction in NISQ-era computing for their potential to reduce quantum resource usage while preserving computational accuracy. In this work, we evaluate two 8-qubit hybrid approximate quantum adders that combine a 2-qubit approximate block, either a pass-through Copy Adder or a CNOT-based design, with a 6-qubit Cuccaro ripple-carry adder. Simulations are conducted using IBM's Qiskit framework under realistic noise models, including bit-flip, depolarizing, and thermal noise. Compared to the exact 8-bit Cuccaro adder, our designs reduce quantum cost and circuit depth by over 20 percent and achieve up to 79.3 percent higher output probability under noisy conditions. These results highlight the robustness and efficiency of approximate logic in noisy quantum environments and confirm its practicality for near-term quantum hardware.
Quantum computing promises unparalleled computational power, but its practical implementation is hampered by quantum noise, which affects the reliability of quantum circuits. This paper addresses the critical challenge of noise classification in NISQ ‘Noisy Intermediate-Scale Quantum’ algorithms, focusing on bit flip, phase flip, and depolarising noise. We introduce a novel balanced quantum noise dataset generated through random quantum circuits, ensuring comprehensive coverage of various noise types and intensities. Additionally, we develop a hybrid quantum-classical machine learning model that achieves over 85% accuracy in classifying bit flip and depolarising noise, and perfect accuracy in detecting phase flip noise under our simulation conditions. Our approach builds on a dual quantum architecture, utilising IBM Qiskit for dataset generation and Pennylane for model training. These simulation results indicate potential improvements for noise-aware modelling and error mitigation; however, we emphasise that translating this performance to physical devices requires further validation due to hardware-specific decoherence and calibration effects.
Qubits with strongly biased noise, in which phase-flip errors are orders of magnitude more frequent than bit-flips, arise both naturally, as in electron and nuclear spins, and by engineering, as in stabilized cat qubits. This noise structure holds the promise of reducing the daunting hardware overhead of fault-tolerant quantum computing, but exploiting it requires physical operations that do not convert frequent phase-flips into rare bit-flips. In this review, we analyze the most prominent fault-tolerant protocols for biased-noise qubits, organized according to the available set of such bias-preserving operations. When this set is restricted to the CZ gate together with preparation and measurement in the X basis, we show that the complexity of the required syndrome extraction gadgets essentially cancels the benefit of the noise bias: at experimentally relevant error rates, one may as well ignore the bias and rely on standard error correction designed for depolarizing noise. The situation changes drastically when a bias-preserving CX gate is available: the hierarchy of errors can then be reflected in the structure of the code, with frequent phase-flips corrected by a dedicated high-threshold code and rare bit-flips by concatenation with a high-rate code. The same hierarchy also enables hardware-efficient preparation of magic states. Finally, as a bias-preserving CX is forbidden in naturally biased platforms and challenging in engineered ones, we present a measurement-based architecture in which a high-fidelity quantum non-demolition readout of multi-qubit Pauli Z operators takes its place, extending these overhead reductions to a much broader range of physical platforms.