Resource-Efficient Cross-Platform Verification with Modular Superconducting Devices
Kieran Dalton, Johannes Knörzer, Finn Hoehne, Yookyung Song, Alexander Flasby, Dante Colao Zanuz, Mohsen Bahrami Panah, Ilya S. Besedin, Jean-Claude Besse, Andreas J. Wallraff
Large-scale quantum computers are expected to benefit from modular architectures. Validating the capabilities of modular devices requires benchmarking strategies that assess performance within and between modules. In this work, we evaluate cross-platform verification protocols, which are critical for quantifying how accurately different modules prepare the same quantum state—a key requirement for modular scalability and system-wide consistency. We demonstrate these algorithms using a six-qubit flip-chip superconducting quantum device consisting of two 3-qubit modules on a single carrier chip, with connectivity for intra- and intermodule entanglement. We examine how the resource requirements of protocols relying solely on classical communication between modules scale exponentially with qubit number, and demonstrate that introducing an intermodule two-qubit gate enables subexponential scaling in cross-platform verification. This approach reduces the number of repetitions required by a factor of 4 for three-qubit states, with greater reductions projected for larger and higher-fidelity devices.
Large-scale quantum computers are expected to benefit from modular architectures. Validating the capabilities of modular devices requires benchmarking strategies that assess performance within and between modules. In this work, we evaluate cross-platform verification protocols, which are critical for quantifying how accurately different modules prepare the same quantum state—a key requirement for modular scalability and system-wide consistency. We demonstrate these algorithms using a six-qubit flip-chip superconducting quantum device consisting of two 3-qubit modules on a single carrier chip, with connectivity for intra- and intermodule entanglement. We examine how the resource requirements of protocols relying solely on classical communication between modules scale exponentially with qubit number, and demonstrate that introducing an intermodule two-qubit gate enables subexponential scaling in cross-platform verification. This approach reduces the number of repetitions required by a factor of 4 for three-qubit states, with greater reductions projected for larger and higher-fidelity devices.
As quantum devices continue to scale, distributed quantum computing emerges as a promising strategy for executing large-scale tasks across modular quantum processors. A central challenge in this paradigm is verifying the correctness of computational outcomes when subcircuits are executed independently following circuit cutting. Here we propose a cross-platform fidelity estimation algorithm tailored for modular architectures. Our method achieves substantial reductions in sample complexity compared to previous approaches designed for single-processor systems. We experimentally implement the protocol on modular superconducting quantum processors with up to 6 qubits to verify the similarity of two 11-qubit GHZ states. Beyond verification, we show that our algorithm enables a federated quantum kernel method that preserves data privacy. As a proof of concept, we apply it to a 5-qubit quantum phase learning task using six 3-qubit modules, successfully extracting phase information with just eight training samples. These results establish a practical path for scalable verification and trustworthy quantum machine learning of modular quantum processors.
Abstract Three-dimensional integration technologies such as flip-chip bonding are a key prerequisite to realize large-scale superconducting quantum processors. Modular architectures, in which circuit elements are spread over multiple chips, can further improve scalability and performance by enabling the integration of elements with different substrates or fabrication processes, by increasing the fabrication yield of completed devices, and by physically separating the qubits onto distinct modules to avoid correlated errors mediated by a common substrate. We present a design for a multi-chip module comprising one carrier chip and four qubit modules. Measuring two of the qubits, we analyze the readout performance, finding a mean three-level state-assignment error of 9×10−3 9 × 10 − 3 in 200 ns. We calibrate single-qubit gates and measure a mean simultaneous randomized benchmarking error of 6×10−4 6 × 10 − 4 , consistent with the coherence times of the qubits. Using a wiring-efficient static inter-module coupler featuring galvanic inter-chip transitions, we demonstrate a controlled-Z two-qubit gate in 100 ns with an error of 7×10−3 7 × 10 − 3 extracted from interleaved randomized benchmarking. Three-dimensional integration, as presented here, will continue to contribute to improving the performance of gates and readout as well as increasing the qubit count in future superconducting quantum processors.
In addition to striving to assemble more and more qubits in a single monolithic quantum device, taking a modular design strategy may mitigate numerous engineering challenges for achieving large-scalable quantum processors with superconducting qubits. Nevertheless, a major challenge in the modular quantum device is how to realize high-fidelity entanglement operations on qubits housed in different modules while preserving the desired isolation between modules. In this work, we propose a conceptual design of a modular quantum device, where nearby modules are spatially separated by centimeters. In principle, each module can contain tens of superconducting qubits and can be separately fabricated, characterized, packaged, and replaced. By introducing a bridge module between nearby qubit modules and taking the coupling scheme utilizing a tunable bus, tunable coupling of qubits that are housed in nearby qubit modules could be realized. Given physically reasonable assumptions, we expect that sub-100-ns two-qubit gates for qubits housed in nearby modules, which are spatially separated by more than two centimeters could be obtained. In this way, the inter-module gate operations are promising to be implemented with gate performance comparable with that of intra-module gate operations. Moreover, with the help of through-silicon vias technologies, this long-range coupling scheme may also allow one to implement inter-module couplers in a multi-chip stacked processor. Thus, the tunable longer-range coupling scheme and the proposed modular architecture may provide a promising foundation for solving challenges toward large-scale quantum information processing with superconducting qubits.
The path toward practical superconducting quantum processors requires the integration of a large number of high-performance qubits. Modular architectures could offer a way to address the scaling limitations of monolithic designs by partitioning a large quantum processor into physically separated modules, or chiplets, linked through long-range interconnects. In this context, although fluxonium qubits have emerged as a compelling platform for quantum computing due to their long coherence times and high-fidelity gates, existing coupling schemes remain restricted to qubits in close proximity on a single chip. This limitation inherently precludes the long-range interconnects essential for modular integration. In this work, we propose a long-range tunable coupler designed to interconnect fluxonium qubits separated by more than one centimeter, thereby supporting the realization of modular fluxonium quantum processors. Under realistic assumptions, the proposed coupler has the potential to achieve inter-module two-qubit gate performance, specifically sub-100-ns gates with intrinsic errors below 10−4, comparable to that of intra-module (intra-chiplet) gates, while enabling modular integration with low quantum crosstalk, a key requirement for scalable systems. We further discuss the integration of this coupler into modular fluxonium lattices and explore its feasibility for achieving the higher connectivity and longer coupling range required for complex quantum error correction codes. This work could contribute to the development of large-scale fluxonium quantum processors by bridging their demonstrated potential with modular scalability.
This thesis mainly summarizes two experiments that relate to building a quantum computer out of superconducting transmon qubits. Transmon qubits have emerged as one of the foremost solid state qubits, realizing processors with more than ten qubits and demonstrating small scale quantum algorithms as well as quantum error correction schemes. Right now, there is a race between different academic and industry research groups to scale up transmon qubit processors. The first experiment was a demonstration of qubit control by selective broadcasting in order to reduce the scaling of expensive electronics with the number of qubits for individual single-qubit control. We demonstrated that we can bring two transmon qubits to the same frequency (combining fabrication accuracy and in-situ fine tuning) and use the same hardware to control both, routing the pulses with a nanosecond-timescale vector switch matrix. Despite the compromises required by this technique, we show a scalable path to single qubit control beyond the threshold required for quantum error correction. In benchmarking, we take into account gate leakage due to the fact that transmons are fundamentally multi-level systems. In the second experiment we establish entanglement between two transmon qubits on different chips. We use an entanglement by measurement scheme and demonstrate that we can overcome minor fabrication imperfections by shaping our measurement pulses. Ultimately, performance is mainly limited by photon loss between the chips and up to the amplification chain. This entanglement mediated by traveling photons could be used to make a distributed transmon processor where computations are spread across several chip modules. This modularity could enable connectivities that cannot be realized on chip and ease fabrication requirements, as modules could be individually fabricated and selected. Thus, both of these experiments fit into the larger effort to converge on the hardware, control equipment and architecture of a future large-scale transmon quantum computer. Other experiments I contributed to are summarized in the conclusion chapter to show the diverse physics that can be studied in cQED experiments.
Modular quantum processor architectures are envisioned as a promising solution for the scalability of quantum computing systems beyond the Noisy Intermediate Scale Quantum (NISQ) era. Based upon interconnecting tens to hundreds of quantum processors (i.e cores) via quantum coherent and classical links, this approach unravels the pressing limitations of densely qubit-packed monolithic processors, mainly by mitigating the requirements of qubit control and enhancing qubit isolation. Therefore, this new architectural design enables executing large-scale algorithms in a distributed manner. In order to assess the performance and optimize such architectures, it is crucial to analyze the quantum state transfers occurring via inter-core communication networks, referred to as inter-core qubit traffic. This would provide insights to improve the software and hardware stack for multi-core quantum computers. To this aim, we present a characterization of the spatio-temporal inter-core qubit traffic for different large-scale quantum algorithms. The programs are compiled on an all-to-all connected multi-core architecture that supports up to around 1000 qubits. We characterize the qubit traffic based on multiple performance metrics to assess the computational process and the communication overhead. Based on the showcased results, we conclude on the parallelization and scalability of presented algorithms, qualitatively evaluate the resource requirements as we scale circuit sizes, and lay the foundations of application-oriented benchmarking of large-scale multi-core architectures.