Characterizing the Inter-Core Qubit Traffic in Large-Scale Quantum Modular Architectures
Sahar Ben Rached, Isaac Lopez Agudo, Santiago Rodrigo, Medina Bandić, Artur García-Sáez, Sebastian Feld, Hans van Someren, Eduard Alarcón, Carmen G. Almudéver, Sergi Abadal
Modular quantum processor architectures are envisioned as a promising solution for the scalability of quantum computing systems beyond the Noisy Intermediate Scale Quantum (NISQ) era. Based upon interconnecting tens to hundreds of quantum processors (i.e cores) via quantum coherent and classical links, this approach unravels the pressing limitations of densely qubit-packed monolithic processors, mainly by mitigating the requirements of qubit control and enhancing qubit isolation. Therefore, this new architectural design enables executing large-scale algorithms in a distributed manner. In order to assess the performance and optimize such architectures, it is crucial to analyze the quantum state transfers occurring via inter-core communication networks, referred to as inter-core qubit traffic. This would provide insights to improve the software and hardware stack for multi-core quantum computers. To this aim, we present a characterization of the spatio-temporal inter-core qubit traffic for different large-scale quantum algorithms. The programs are compiled on an all-to-all connected multi-core architecture that supports up to around 1000 qubits. We characterize the qubit traffic based on multiple performance metrics to assess the computational process and the communication overhead. Based on the showcased results, we conclude on the parallelization and scalability of presented algorithms, qualitatively evaluate the resource requirements as we scale circuit sizes, and lay the foundations of application-oriented benchmarking of large-scale multi-core architectures.
Modular quantum processor architectures are envisioned as a promising solution for the scalability of quantum computing systems beyond the Noisy Intermediate Scale Quantum (NISQ) era. Based upon interconnecting tens to hundreds of quantum processors (i.e cores) via quantum coherent and classical links, this approach unravels the pressing limitations of densely qubit-packed monolithic processors, mainly by mitigating the requirements of qubit control and enhancing qubit isolation. Therefore, this new architectural design enables executing large-scale algorithms in a distributed manner. In order to assess the performance and optimize such architectures, it is crucial to analyze the quantum state transfers occurring via inter-core communication networks, referred to as inter-core qubit traffic. This would provide insights to improve the software and hardware stack for multi-core quantum computers. To this aim, we present a characterization of the spatio-temporal inter-core qubit traffic for different large-scale quantum algorithms. The programs are compiled on an all-to-all connected multi-core architecture that supports up to around 1000 qubits. We characterize the qubit traffic based on multiple performance metrics to assess the computational process and the communication overhead. Based on the showcased results, we conclude on the parallelization and scalability of presented algorithms, qualitatively evaluate the resource requirements as we scale circuit sizes, and lay the foundations of application-oriented benchmarking of large-scale multi-core architectures.
Quantum many-core processors are envisioned as the ultimate solution for the scalability of quantum computers. Based upon Noisy Intermediate-Scale Quantum (NISQ) chips interconnected in a sort of quantum intranet, they enable large algorithms to be executed on current and close future technology. In order to optimize such architectures, it is crucial to develop tools that allow specific design space explorations. To this aim, in this paper we present a technique to perform a spatio-temporal characterization of quantum circuits running in multi-chip quantum computers. Specifically, we focus on the analysis of the qubit traffic resulting from operations that involve qubits residing in different cores, and hence quantum communication across chips, while also giving importance to the amount of intra-core operations that occur in between those communications. Using specific multi-core performance metrics and a complete set of benchmarks, our analysis showcases the opportunities that the proposed approach may provide to guide the design of multi-core quantum computers and their interconnects.
Modular architectures are a promising approach to scaling quantum computers beyond the limits of monolithic designs. However, non-local communications between different quantum processors might significantly impact overall system performance. In this work, we investigate the role of the network infrastructure in modular quantum computing architectures, focusing on coherence loss due to communication constraints. We analyze the impact of classical network latency on quantum teleportation and identify conditions under which it becomes a bottleneck. Additionally, we study different network topologies and assess how communication resources affect the number and parallelization of inter-core communications. Finally, we conduct a full-stack evaluation of the architecture under varying communication parameters, demonstrating how these factors influence the overall system performance. The results show that classical communication does not become a bottleneck for systems exceeding one million qubits, given current technology assumptions, even with modest clock frequencies and parallel wired interconnects. Additionally, increasing quantum communication resources generally shortens execution time, although it may introduce additional communication overhead. The optimal number of quantum links between QCores depends on both the algorithm being executed and the chosen inter-core topology. Our findings offer valuable guidance for designing modular architectures, enabling scalable quantum computing.
Current monolithic quantum computer architectures have limited scalability. One promising approach for scaling them up is to use a modular or multi-core architecture, in which different quantum processors (cores) are connected via quantum and classical links. This new architectural design poses new challenges such as the expensive inter-core communication. To reduce these movements when executing a quantum algorithm, an efficient mapping technique is required. In this paper, a detailed critical discussion of the quantum circuit mapping problem for multi-core quantum computing architectures is provided. In addition, we further explore the performance of a mapping method, which is formulated as a partitioning over time graph problem, by performing an architectural scalability analysis.
Quantum computing represents a paradigm shift in computation, offering the potential to solve complex problems intractable for classical computers. Although current quantum processors already consist of a few hundred qubits, their scalability remains a significant challenge. Modular quantum computing architectures have emerged as a promising approach to scale up quantum computing systems. This article delves into the critical aspects of distributed multi-core quantum computing, focusing on quantum circuit mapping, a fundamental task to successfully execute quantum algorithms across cores while minimizing inter-core communications. We derive the theoretical bounds on the number of non-local communications needed for random quantum circuits and introduce the Hungarian Qubit Assignment (HQA) algorithm, a multi-core mapping algorithm designed to optimize qubit assignments to cores with the aim of reducing inter-core communications. Our exhaustive evaluation of HQA against state-of-the-art circuit mapping algorithms for modular architectures reveals a 4.9× and 1.6× improvement in terms of execution time and non-local communications, respectively, compared to the best-performing algorithm. HQA emerges as a very promising scalable approach for mapping quantum circuits into multi-core architectures, positioning it as a valuable tool for harnessing the potential of quantum computing at scale.
Modular quantum computing architectures are a promising alternative to monolithic QPU (Quantum Processing Unit) designs for scaling up quantum devices. They refer to a set of interconnected QPUs or cores consisting of tightly coupled quantum bits that can communicate via quantum-coherent and classical links. In multi-core architectures, it is crucial to minimize the amount of communication between cores when executing an algorithm. Therefore, mapping a quantum circuit onto a modular architecture involves finding an optimal assignment of logical qubits (qubits in the quantum circuit) to different cores with the aim to minimize the number of expensive inter-core operations while adhering to given hardware constraints. In this paper, we propose for the first time a Quadratic Unconstrained Binary Optimization (QUBO) technique to encode the problem and the solution for both qubit allocation and inter-core communication costs in binary decision variables. To this end, the quantum circuit is split into slices, and qubit assignment is formulated as a graph partitioning problem for each circuit slice. The costly inter-core communication is reduced by penalizing inter-core qubit communications. The final solution is obtained by minimizing the overall cost across all circuit slices. To evaluate the effectiveness of our approach, we conduct a detailed analysis using a representative set of benchmarks having a high number of qubits on two different multi-core architectures. Our method showed promising results and performed exceptionally well with very dense and highly-parallelized circuits that require on average 0.78 inter-core communications per two-qubit gate.
The scalability of quantum computing is constrained by the physical and architectural limitations of monolithic quantum processors. Modular multi-core quantum architectures, which interconnect multiple quantum cores (QCs) via classical and quantum-coherent links, offer a promising alternative to address these challenges. However, transitioning to a modular architecture introduces communication overhead, where classical communication plays a crucial role in executing quantum algorithms by transmitting measurement outcomes and synchronizing operations across QCs. Understanding the impact of classical communication on execution time is therefore essential for optimizing system performance. In this work, we introduce qcomm , an open-source simulator designed to evaluate the role of classical communication in modular quantum computing architectures. qcomm provides a high-level execution and timing model that captures the interplay between quantum gate execution, entanglement distribution, teleportation protocols, and classical communication latency. We conduct an extensive experimental analysis to quantify the impact of classical communication bandwidth, interconnect types, and quantum circuit mapping strategies on overall execution time. Furthermore, we assess classical communication overhead when executing real quantum benchmarks mapped onto a cryogenically-controlled multi-core quantum system. Our results show that, while classical communication is generally not the dominant contributor to execution time, its impact becomes increasingly relevant in optimized scenarios—such as improved quantum technology, large-scale interconnects, or communication-aware circuit mappings. These findings provide useful insights for the design of scalable modular quantum architectures and highlight the importance of evaluating classical communication as a performance-limiting factor in future systems.